Gate Driving Circuit with Capacitive Voltage Smoothing
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Solution Overview
Problem
Existing display apparatuses face challenges in stabilizing the output of gate signals due to stress on transistors caused by multi-stage voltage changes, leading to instability in the gate driving circuit.
Innovation Solution
A small-sized gate driving circuit is designed with specific transistor configurations and capacitors to manage voltage levels, including P-type and N-type transistors, and capacitors to stabilize the output of gate signals, reducing stress on transistors by managing voltage transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate driving circuit is used, then the circuit can output gate signals, but the transistors experience stress from multi-stage voltage changes causing signal instability
Solution Approach 1:
The patent applies preliminary action by using a first capacitor to advance the voltage transition at the first node before it reaches the second node. This pre-charging or pre-discharging of the first capacitor reduces the voltage step height that the second transistor must handle, thereby reducing transistor stress while maintaining signal stability.
Solution Approach 2:
The patent introduces an intermediary approach by inserting a first capacitor between the first node and second node. This capacitor acts as a voltage buffer or mediator that smooths the voltage transition, reducing the direct voltage stress on the second transistor while still enabling the necessary signal propagation.
2Reliability
If transistor configurations are added to manage voltage levels, then transistor stress is reduced, but the device area increases
Solution Approach 1:
The patent merges the voltage management function into the existing transistor structure by utilizing the first and second capacitors in conjunction with the transistors' natural switching behavior. This integration allows voltage level management without requiring entirely separate dedicated circuits, thereby minimizing the additional area occupied.
Solution Approach 2:
The patent changes the electrical parameters (voltage levels, timing) through the strategic placement of capacitors to achieve voltage management. By controlling the timing and magnitude of voltage transitions through capacitor charging and discharging characteristics, the circuit achieves stable operation without adding significant physical area.
3Reliability
If capacitors are added to stabilize voltage levels, then transistor stress is reduced, but the circuit complexity increases
Solution Approach 1:
The patent uses preliminary action where the first capacitor is charged or discharged in advance during a previous clock cycle, preparing the voltage state before the current switching event. This eliminates the need for complex real-time voltage regulation logic during the actual signal transition.
Solution Approach 2:
The capacitors automatically charge and discharge based on the clock signal timing and voltage differences, providing self-regulating voltage management without requiring additional control logic or complex circuitry. The circuit uses its own operational signals to drive the capacitor behavior.
Data Source
AI summary
A driving circuit including a plurality of stages to output gate signals to pixels, each of the stages includes: a first transistor between a first terminal and a first node and including a gate connected to a first clock terminal, wherein a start signal is input to the first terminal and a first clock signal is input to the first clock terminal; a second transistor between the first node and a second node and including a gate connected to the first clock terminal; a third transistor between a second clock terminal and the first node and including a gate connected to the first terminal, wherein a second clock signal is input to the second clock terminal; a pull-up transistor between a second terminal and an output terminal and including a gate connected to the first clock terminal; and a pull-down transistor between the output terminal and the second clock terminal.