Gate Driving Circuit Placement for Bezel Minimization

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Solution Overview

Problem

Existing display apparatuses face challenges with increased bezel areas and gate pulse delay due to the placement of shift registers and lack of structures to reduce parasitic capacitance, limiting the miniaturization of display panels and efficiency.

Innovation Solution

The display apparatus is designed with gate driving circuits in non-display areas other than the pad part, featuring connection lines on a different layer than the gate lines, which reduces the non-display areas and minimizes parasitic capacitance, allowing for a more compact design and reduced bezel size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the shift register is disposed in each of the left and right non-display areas using the double feeding method, then the gate pulse can be supplied to the display panel, but the design area of the shift register increases to increase the left and right bezel areas

Engineering Contradiction:
Improvegate pulse supplyVSAvoidbezel area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the shift register function from the traditional left and right non-display areas and relocates it to the bottom non-display area. This extraction allows the left and right bezel areas to be minimized while maintaining the gate pulse supply function through the gate-in-panel structure where the shift register is integrated into the bottom edge of the display panel.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the spatial dimension for placing the shift register from horizontal (left and right sides) to vertical (bottom edge). By positioning the shift register in the bottom non-display area and using connection lines extending vertically to connect to gate lines, the patent achieves gate pulse supply without increasing horizontal bezel dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the interlacing method is applied to a large display panel, then the gate pulse can be supplied, but the delay of the gate pulse increases in a direction distancing from the input terminal

Engineering Contradiction:
Improvegate pulse supplyVSAvoidgate pulse delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the gate lines into multiple groups, with each group connected to a separate shift register unit positioned at the bottom edge. This segmentation allows parallel operation of multiple shift register units, reducing the overall gate pulse delay by distributing the scanning function across multiple independent units rather than using a single sequential interlacing method.

Inventive Principle:
Principle #1Segmentation

3Reliability

If at least one of four side surfaces of a front cover surrounds the display panel at a front portion, then the pad part exposed at the front surface is covered, but it is difficult to decrease the size of the front bezel

Engineering Contradiction:
Improvepad part coverageVSAvoidfront bezel size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the pad part from the front surface location and relocates it to the bottom non-display area where it can be covered by the front cover's bottom surface rather than requiring side surfaces to surround the display panel. This extraction allows the front bezel size to be minimized while maintaining proper pad part coverage and protection.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11730023B2Display apparatus for minimizing width of bezel
Publication Date: 2023.08.15 LG DISPLAY CO LTD
  • US11730023B2 patent drawing
  • US11730023B2 patent drawing
  • US11730023B2 patent drawing

AI summary

Disclosed is a display apparatus in which a gate driving circuit is disposed in each of non-display areas other than a non-display area including a pad part among a plurality of non-display areas, and a plurality of connection lines provided on a layer differing from a plurality of gate lines and connected to the gate lines are provided.