Gate Driving Circuit Bezel Reduction via Stage Segmentation
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Solution Overview
Problem
The challenge is to reduce the bezel area in display devices while managing the increasing number of signal lines in the bezel area, which complicates the design of compact display devices.
Innovation Solution
A gate driving circuit with a small-area structure is implemented, featuring multiple stage circuits connected to clock signal lines that output scan and carry signals, including buffer groups, logic parts for image driving, and sensing parts for sub-pixel characteristic sensing, with specific connections to reduce the number of clock signal lines and thereby minimize the bezel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of signal lines in the bezel area is increased to support more stage circuits, then the functionality and performance of the display device is improved, but the bezel area becomes larger and it becomes difficult to reduce the bezel width
Solution Approach 1:
The gate driving circuit is divided into multiple independent stage circuits (first stage circuit, second stage circuit, third stage circuit), each handling specific scan lines and clock signal lines. This segmentation allows each stage to be optimized independently, reducing the overall signal line requirements in the bezel area while maintaining full functionality.
Solution Approach 2:
Each stage circuit is designed to perform multiple functions: driving display during the display driving period and sensing sub-pixel characteristics during the sensing driving period. This multi-functionality reduces the need for separate dedicated signal lines for different purposes, thereby reducing the total number of signal lines required in the bezel area.
2Speed
If more clock signal lines are used to drive more stage circuits, then the scanning speed and coverage are improved, but the number of signal lines increases making compact design difficult
Solution Approach 1:
Instead of increasing the number of clock signal lines to improve scanning speed, the patent inverts the approach by using fewer clock signal lines with optimized timing and phase control. The first and second carry clock signal lines are strategically used to control multiple stage circuits, achieving high scanning speed through intelligent signal management rather than brute-force signal multiplication.
Solution Approach 2:
The patent changes the timing parameters and phase relationships of the clock signals to optimize performance. By carefully controlling the timing of the first and second carry clock signal lines and their relationship with the scan clock signal lines, the system achieves improved scanning speed without increasing the number of physical signal lines.
Data Source
AI summary
Disclosed herein are a gate driving circuit having a small-area structure and a display device, and more specifically, each of a plurality of stage circuits included in the gate driving circuit includes a sensing part, a logic part, and a buffer group, first to fourth scan clock signals and a first carry clock signal are electrically connected to a first stage circuit, and fifth to eighth scan clock signals and a second carry clock signal are electrically connected to a second stage circuit.