Gate Driving Circuit Parasitic Capacitance Compensation
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Solution Overview
Problem
Integrated gate driving circuits in LCDs experience noise due to parasitic capacitance and high temperatures, leading to abnormal gate-on signals and display defects.
Innovation Solution
The gate driving circuit design includes a pull-up section with a ninth transistor having a larger width-to-length ratio to reduce voltage ripple at the control electrode, preventing abnormal gate-on signals by increasing the parasitic capacitance between the gate and source electrodes, which compensates for the parasitic capacitance between the gate and drain electrodes, thereby reducing total ripple and enhancing the low temperature driving margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate driving circuit is integrated directly on the display substrate to decrease LCD size and increase productivity, then manufacturing efficiency and device compactness are improved, but noise is generated due to parasitic capacitance between clock signal and gate of pull-up transistor, causing abnormal gate-on signals and display defects
Solution Approach 1:
The patent extracts and eliminates the parasitic capacitance Cgd between the clock signal and gate of pull-up transistor by modifying the circuit topology. This is achieved by reconfiguring the connection between clock terminals and pull-up transistor gates, effectively removing the harmful capacitive coupling that causes noise and abnormal gate-on signals while maintaining the integrated circuit structure.
Solution Approach 2:
The patent converts the harmful parasitic capacitance effect into a beneficial configuration by strategically placing capacitive elements to compensate for the parasitic effects. The circuit design utilizes the inherent parasitic capacitances in a controlled manner to stabilize the gate voltage and prevent abnormal turning on, transforming the previously harmful effect into a stabilizing mechanism.
2Adaptability or versatility
If the gate driving circuit is operated at high temperatures, then the LCD can function in various environmental conditions, but the transistor's leakage current increases due to high temperature, causing the pull-up transistor to turn on abnormally
Solution Approach 1:
The patent applies preliminary anti-action by designing the circuit to pre-compensate for high-temperature effects. The modified circuit topology and threshold voltage settings are configured in advance to counteract the increased leakage current that occurs at high temperatures, preventing the pull-up transistor from abnormally turning on and maintaining signal stability across temperature variations.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the threshold voltage characteristics and transistor dimensions to optimize performance across temperature ranges. The circuit design incorporates specific width-to-length ratios and voltage levels that maintain proper transistor switching behavior both at low and high temperatures, ensuring reliable operation under varying environmental conditions.
3Power
If the pull-up transistor turns on due to parasitic capacitance and leakage current, then the gate voltage increases, but this causes intermittent abnormal gate-on signals and display defects
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a modified circuit configuration that mediates between the clock signal and the pull-up transistor gate. This intermediary structure controls the timing and level of voltage applied to the gate, preventing premature or abnormal turning on while ensuring proper activation during normal operation, thereby eliminating display defects caused by spurious gate signals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively decreases the ripple at the control electrode, preventing abnormal gate-on signals and reducing display defects, while improving the low temperature driving margin and reliability of the gate driving circuit.
Implementation Method 1
noise can be generated in the form of an abnormal gate-on signal occurring in gate-off time. The noise is generated due to parasitic capacitance (Cgd) between a clock signal and the gate of a pull-up transistor. This capacitance serves to increase the transistor's gate voltage when the transistor is supposed to be off.
Data Source
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AI summary
In a gate driving circuit and a display apparatus, the gate driving circuit comprises a plurality of stages. At least one of the stages comprises a pull-up section responsive to a first node signal; a pull-down section responsive to a second input signal; a discharging section discharging the first node signal in response to the second input signal; a first holding section responsive to the first clock signal, maintaining the first node signal at the off-voltage; and a second holding section responsive to the second clock signal, maintaining the first node signal at the off-voltage. The second holding section has a greater transistor width-to-length ratio than the first holding section. Therefore, an abnormal gate-on signal is less likely to occur, reducing driving defects of the display apparatus.