Gate Driving Circuit with Capacitive Node Control for Narrow Bezel Displays
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Solution Overview
Problem
Existing gate driving circuits face challenges in reducing output deviation and size to achieve a narrow bezel in display devices, particularly when multiple scan signals are output from a single stage, which affects the performance and resolution of display panels.
Innovation Solution
A gate driving circuit with stage circuits connected in a dependent manner, utilizing logic controllers and output buffers with capacitors to control voltage nodes and output clock signals, allowing for reduced output deviation and size, enabling efficient scan signal distribution across multiple gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If one stage sequentially outputs multiple scan signals to reduce bezel width, then the device size is reduced, but output deviation of scan signals occurs
Solution Approach 1:
The gate driving circuit is divided into multiple stage circuits (first stage circuit, second stage circuit, etc.), where each stage outputs scan signals to specific gate lines. This segmentation allows parallel operation of multiple stages, eliminating output deviation while enabling coverage of multiple gate lines without increasing bezel width.
Solution Approach 2:
Multiple stage circuits are combined to operate simultaneously, with each stage handling a portion of the gate lines. This merging approach maintains signal consistency across all outputs while achieving the functionality of driving multiple gate lines, thus reducing bezel width without sacrificing signal precision.
2Adaptability or versatility
If multiple output buffers are used to drive multiple gate lines, then scan signal distribution is improved, but circuit complexity increases
Solution Approach 1:
Each stage circuit is designed with universal functionality to output multiple scan signals simultaneously to different gate lines. The stage circuits use common control mechanisms and similar structural configurations, allowing them to perform multiple functions without requiring entirely separate circuit paths for each gate line, thus reducing overall complexity.
Solution Approach 2:
The stage circuits are designed with equivalent control conditions and signal levels, ensuring that all output buffers operate under the same potential conditions. This equipotential design simplifies the control logic and reduces the complexity of signal management across multiple outputs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces output deviation and size, enhancing the resolution and enabling a narrower bezel in display devices by improving the control and distribution of scan signals, thus addressing the limitations of existing gate driving circuits.
Implementation Method 1
a plurality of capacitors disposed between the first node and the output node of some of the j output buffers
Data Source
AI summary
Disclosed is a gate driving circuit comprising a plurality of stage circuits dependently connected to each other and configured to output ‘j’ output signals ('j′ is an integer of 2 or more), wherein each of the plurality of stage circuits includes a logic controller for controlling a voltage of each of first and second nodes, and an output circuit unit for outputting each of ‘j’ clock signals as the ‘j’ output signal in response to the voltage of the first node, wherein the output circuit unit includes ‘j’ output buffers for outputting each of the ‘j’ clock signals as the ‘j’ output signal through an output node in response to the voltage of the first node, and a capacitor prepared between the first node and the output node of some of the ‘j’ output buffers.