Gate Driving Circuit Capacitor Structure for Array Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing array substrates for liquid crystal displays face a challenge in maintaining sufficient charging capacity for capacitors, which leads to a deterioration in the output characteristic of the gate driving circuit, resulting in shortened rise time and increased parasitic capacitance.
Innovation Solution
The array substrate is designed with a substrate divided into a display area and a peripheral area, featuring a pixel array and a driving circuit where each stage includes a transistor with a source electrode connected to an output terminal, a channel layer between the gate insulating layer and the source electrode, and a capacitor defined by the gate electrode, source electrode, and gate insulating layer, facilitating contact and enhancing charging capacity without increasing electrode area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the electrode area of the capacitors is increased to enhance charging capacity, then the rise time is improved, but the parasitic capacitance between the capacitor electrode and the common electrode increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming the capacitor electrode and common electrode in different layers separated by an insulating layer. This three-dimensional arrangement allows the electrodes to overlap in the vertical direction while maintaining horizontal separation, thereby increasing charging capacity without increasing the horizontal electrode area that would generate parasitic capacitance.
Solution Approach 2:
The capacitor structure is nested within the transistor structure, where the capacitor electrode is formed using the same conductive material layers as the transistor electrodes. The capacitor is embedded in the peripheral area beneath or alongside the pixel electrodes, allowing efficient use of space and reducing the need for additional electrode area.
2Productivity
If the gate driving circuit is formed on the array substrate to reduce display size, then the productivity is improved, but the output characteristic deteriorates due to insufficient charging capacity
Solution Approach 1:
The gate driving circuit is merged with the pixel array on the same array substrate, forming an integrated structure. The capacitor in each stage of the gate driving circuit is constructed using the same thin-film deposition processes as the pixel electrodes, combining the driving function with the display function in a single substrate fabrication process.
Solution Approach 2:
The patent changes the electrical parameters of the capacitor by adjusting the thickness and dielectric constant of the insulating layer, as well as the overlapping area of the electrodes in the vertical direction. This allows optimization of the charging capacity to provide sufficient rise time for the gate signal while maintaining the integrated structure benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures a sufficient rise time for the gate signal, improving the output characteristic of the gate driving circuit while preventing parasitic capacitance, thus enhancing the overall performance of the display apparatus.
Implementation Method 1
a capacitor defined by a gate electrode of the first transistor, the source electrode, and the portion of the gate insulating layer contacting the source electrode
Data Source
AI summary
An array substrate and a display apparatus including the array substrate are provided. The array substrate includes a substrate divided into a display area and a peripheral area adjacent to the display area. A pixel array is formed on the substrate corresponding to the display area and receives a driving signal. A driving circuit includes a plurality of stages and is formed on the substrate corresponding to the peripheral area. Each of the stages includes a first transistor having a source electrode connected to an output terminal to output the driving signal, a channel layer formed between a gate insulating layer and the source electrode, the channel layer having an opening to facilitate contact between a portion of the gate insulating layer and the source electrode, and a capacitor defined by a gate electrode of the first transistor, the source electrode, and the gate insulating layer contacting the source electrode.