Gate Driving Circuit Clock Signal Line Repair via Redundant Layers
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Solution Overview
Problem
The increasing resolution and density of gate drive circuits in flat panel display devices lead to narrower clock signal lines, making them prone to breakage, which existing technologies struggle to effectively repair.
Innovation Solution
A multilayer circuit board structure with cascaded GOA units, multiple first and second clock signal lines, connecting lines, and electrostatic protection sub-circuits, where second clock signal lines can replace broken first clock signal lines, and connecting lines are arranged on different layers to intersect and connect for repair, ensuring electrostatic protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of display devices is increased and the density of gate drive circuits is increased, then the display quality and integration are improved, but the clock signal lines become narrower and more prone to breakage
Solution Approach 1:
The patent applies preliminary action by pre-configuring redundant second clock signal lines and connecting lines in the circuit board layer structure before any breakage occurs. When a first clock signal line breaks, the system can immediately switch to the pre-prepared second clock signal line through the connecting lines, avoiding display failure without requiring real-time repair actions.
Solution Approach 2:
The patent implements beforehand cushioning by creating a protective redundant clock signal line system that cushions against the harmful effect of line breakage. The second clock signal lines and connecting lines are designed in advance to compensate for potential failures, ensuring continuous operation even when first clock signal lines are damaged.
2Reliability
If redundant clock signal lines and connecting lines are added for repair capability, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent applies another dimension by utilizing vertical layering in the circuit board structure. The first and second clock signal lines are arranged in different layers, with connecting lines traversing between layers. This three-dimensional arrangement accommodates redundant pathways without significantly increasing the planar footprint, managing complexity through spatial optimization.
Solution Approach 2:
The connecting lines serve multiple functions: they provide electrostatic protection for the first clock signal lines and simultaneously serve as switchable pathways to connect second clock signal lines when breakage occurs. This multi-functionality reduces the need for separate dedicated repair components, thereby controlling device complexity while maintaining reliability.
3Ease of repair
If connecting lines are arranged on different layers to enable repair, then the repair capability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes the vertical dimension in multi-layer circuit board construction to arrange connecting lines and clock signal lines on different layers. This approach enables repair functionality through inter-layer connections while leveraging established multi-layer PCB manufacturing techniques, which already have standardized precision requirements and processes for handling multi-layer alignment.
Data Source
AI summary
The present disclosure relates to a gate drive circuit. The gate drive circuit includes: cascaded GOA units, first clock signal lines, second clock signal lines, connecting lines and electrostatic protection sub-circuits. The first clock signal lines are used to provide various clock signals to the GOA units. The second clock signal lines are used to, when any of the clock signal lines is broken, replace the broken clock signal line to transmit a corresponding clock signal. The electrostatic protection sub-circuits are electrically connected to corresponding first clock signal lines or corresponding second clock signal lines through the connecting lines. Orthographic projections of the connecting lines on a plane where corresponding first clock signal lines or corresponding second clock signal lines are located intersect with the corresponding first clock signal lines and the corresponding second clock signal lines, respectively.