Gate Driving Circuit Signal Discharge Timing for Display Panels
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Solution Overview
Problem
As display panel sizes increase, the longer first horizontal period leads to gate signal delay, causing deterioration of display images due to the existing gate driving circuit's inability to efficiently manage gate signals effectively.
Innovation Solution
The proposed gate driving circuit incorporates a k-th stage that receives clock and carry signals, along with different voltage levels, to output gate and carry signals, utilizing a configuration of output units, control units, and discharge units to manage signal timing and voltage levels, thereby reducing gate signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the display panel size increases, then the display area is enlarged, but the first horizontal period becomes longer causing gate signal delay
Solution Approach 1:
The gate driving circuit dynamically adjusts the discharge timing of gate signals based on the panel size and horizontal period. The circuit uses variable discharge control where the discharge timing is adjusted according to the clock signal phase and carry signal timing, allowing the circuit to adapt to different panel sizes and maintain proper signal timing without fixed discharge schedules
Solution Approach 2:
The circuit changes operational parameters including voltage levels (first voltage, second voltage, third voltage with different relationships), clock signal frequencies, and discharge timing parameters. By adjusting these parameters based on panel characteristics, the circuit optimizes gate signal delivery speed to compensate for increased signal path length in larger displays
2Duration of action of moving object
If the first horizontal period becomes longer, then the display panel can be larger, but gate signal delay occurs causing display image deterioration
Solution Approach 1:
The gate driving circuit implements feedback mechanisms where the discharge of each gate signal is controlled by carry signals from subsequent stages. This feedback loop allows the circuit to monitor and adjust discharge timing dynamically, ensuring that gate signals are discharged at optimal moments to maintain image quality even with extended horizontal periods in larger panels
Solution Approach 2:
The circuit performs preliminary discharge actions for gate signals based on predicted timing requirements. By using clock signals and carry signals to pre-coordinate discharge timing before the actual gate signal needs to be delivered, the circuit ensures that signals are ready and timed correctly for the extended horizontal periods required by larger displays
Data Source
AI summary
A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k−1)th carry signal from a (k−1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.