Gate Driving Circuit for Flat Display Uniformity
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Solution Overview
Problem
Large-sized flat display devices face challenges in maintaining displaying uniformity due to feed-through effects caused by capacitive coupling, which result in uneven voltage levels across pixels, especially in the vertical direction, as existing solutions only improve horizontal uniformity while worsening vertical uniformity.
Innovation Solution
The implementation of a control method and circuit that generate two different gate high level voltage signals with varying falling edge durations for scanning lines, allowing for differential compensation of feed-through voltages across the display panel, thereby addressing both horizontal and vertical uniformity issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the refresh frequency is increased to maintain displaying uniformity in large-sized displays, then the displaying uniformity is improved, but the power consumption increases
Solution Approach 1:
The patent applies different gate high level voltages to different gate driving units based on their positions in the display panel. Specifically, gate driving units in the vertical direction are assigned different voltage levels (e.g., first gate high level voltage to first gate driving units, second gate high level voltage to second gate driving units) to compensate for position-dependent feed-through effects, thereby achieving local optimization of displaying uniformity without requiring increased refresh frequency across the entire panel.
Solution Approach 2:
The patent changes the voltage parameter of the scanning signal by providing different gate high level voltages to different gate driving units. This parameter change allows the system to maintain displaying uniformity in large-sized displays without increasing refresh frequency, thus avoiding the power consumption penalty associated with higher refresh rates.
2Manufacturing precision
If different gate high level voltages are provided to different gate driving units, then vertical direction uniformity is improved, but device complexity increases
Solution Approach 1:
The patent segments the gate driving units into multiple groups based on their positions in the display panel. Each segment (first gate driving units, second gate driving units, etc.) is assigned a specific gate high level voltage appropriate for its location. This segmentation approach enables targeted compensation for feed-through effects in different regions while maintaining a manageable control circuit structure through systematic organization.
Solution Approach 2:
The patent introduces asymmetric voltage levels for different gate driving units positioned at different locations in the display panel. Specifically, first gate driving units receive a first gate high level voltage while second gate driving units receive a second gate high level voltage, creating an asymmetric voltage distribution that compensates for position-dependent feed-through effects and achieves uniform display across the panel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform display across the entire panel by providing different compensations for varying feed-through voltages, improving vertical direction uniformity while maintaining horizontal improvements, as proven by experimental results.
Implementation Method 1
a fast transition of voltage level results in a feed-though effect of a capacitor generated by a capacitive coupling effect, which causes a stored voltage of the pixel changed
Data Source
AI summary
In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.