Gate Driving Circuit Dual Scan Without Extra Signal Lines

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Solution Overview

Problem

Existing gate driving circuits require additional signal lines to achieve dual scan capabilities, which complicates the circuit design and increases footprint.

Innovation Solution

A gate driving circuit with n stages, divided into four sets, uses two scan start signals and four clock signals to enable dual scan modes without additional signal lines, by cascading stages and utilizing specific clock signal phases and pulse widths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional signal lines are added to achieve dual scan capability, then the gate driving circuit can perform both forward and reverse scanning, but the circuit complexity and footprint increase

Engineering Contradiction:
Improvedual scan capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The gate driving circuit uses the same signal lines (four clock signals and two scan start signals) to perform both forward scanning and reverse scanning functions. The circuit stages are configured to respond to different combinations of these signals to achieve different scanning directions, making the circuit multi-functional without requiring additional dedicated signal lines for each mode.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The circuit dynamically switches between forward and reverse scanning modes by changing the timing and configuration of the clock signals and scan start signals. The stages are enabled or disabled based on the scanning mode requirement, allowing the same hardware to adapt its behavior dynamically without physical reconfiguration.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If additional signal lines are added to achieve dual scan capability, then the gate driving circuit can perform both forward and reverse scanning, but the circuit footprint increases

Engineering Contradiction:
Improvedual scan capabilityVSAvoidcircuit footprint
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The gate driving circuit uses the same signal lines (four clock signals and two scan start signals) to perform both forward scanning and reverse scanning functions. The circuit stages are configured to respond to different combinations of these signals to achieve different scanning directions, making the circuit multi-functional without requiring additional dedicated signal lines for each mode.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If conventional dual scan circuit design is used, then dual scan functionality is achieved, but the number of signal lines and circuit components increases

Engineering Contradiction:
Improvedual scan functionalityVSAvoidnumber of signal lines
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The gate driving circuit uses the same signal lines (four clock signals and two scan start signals) to perform both forward scanning and reverse scanning functions. The circuit stages are configured to respond to different combinations of these signals to achieve different scanning directions, making the circuit multi-functional without requiring additional dedicated signal lines for each mode.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10255861B2Gate driving circuit, array substrate, display panel and driving method thereof
Publication Date: 2019.04.09 BOE TECHNOLOGY GROUP CO LTD
  • US10255861B2 patent drawing
  • US10255861B2 patent drawing
  • US10255861B2 patent drawing

AI summary

A gate driving circuit is disclosed which includes n stages that are sequentially arranged, n being an integer larger than or equal to 4. The n stages are divided into a first, second, third and fourth sets of stages that are configured to receive respective different combinations of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal. The stages in the first set of stages and the stages in the third set of stages are cascaded with each other, and the stages in the second set of stages and the stages in the fourth set of stages are cascaded with each other. Also disclosed are an array substrate including the gate driving circuit, a display panel including the array substrate, and a driving method of the display panel.