Gate Driving Circuit Output Error Protection

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Solution Overview

Problem

Existing gate driving circuits lack an output error protection function, leading to improper clock signals and erroneous driving signals when input clock signals are all low, causing pixel units to be switched on incorrectly.

Innovation Solution

A control device for the gate driving circuit is introduced, comprising a level shifter and a control module that ensures the output signal is a low level when all input clock signals are low, utilizing a logic unit or timing controller connected with a switching element to provide a low level reference signal to the level shifter, preventing erroneous outputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a level shifter is used to generate clock signals for the gate driving circuit, then the gate driving circuit can receive properly level-shifted clock signals, but when all input clock signals are low, the level shifter may output an improper high level signal causing erroneous driving signals

Engineering Contradiction:
Improveoutput signal correctnessVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A control module is introduced as an intermediary component between the level shifter and the gate driving circuit. This control module monitors the input clock signals and controls the output of the level shifter, preventing erroneous high level signals when all input clock signals are low. The control module acts as a mediator that ensures proper signal transmission without allowing error propagation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The control module implements a feedback mechanism by monitoring the input clock signals and adjusting the output signal accordingly. When all input clock signals are detected to be low, the control module provides feedback to the level shifter to maintain a low level output, preventing the generation of erroneous high level signals. This feedback loop ensures reliable operation of the gate driving circuit.

Inventive Principle:
Principle #23Feedback

2Reliability

If no output error protection function is implemented, then the circuit structure remains simple, but the gate driving circuit may output erroneous driving signals when input clock signals are all low

Engineering Contradiction:
Improvedriving signal accuracyVSAvoidcontrol module addition
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control module serves as an intermediary protective layer between the level shifter and the gate driving circuit. It monitors the operational state and prevents erroneous signals from reaching the gate driving circuit, thereby ensuring driving signal accuracy without requiring fundamental changes to the existing circuit architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The control module provides beforehand cushioning by detecting the condition where all input clock signals are low before erroneous output can occur. It proactively prevents the generation of improper high level signals by controlling the level shifter's output in advance, thus cushioning against potential errors before they affect the gate driving circuit.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS10424235B2Control device for providing output error protection function for gate driving circuit, display panel and display device
Publication Date: 2019.09.24 BOE TECHNOLOGY GROUP CO LTD
  • US10424235B2 patent drawing
  • US10424235B2 patent drawing
  • US10424235B2 patent drawing

AI summary

The embodiments of the application disclose a control device for a gate driving circuit, a display panel and a display device. The control device for a gate driving circuit provided in the embodiment comprises a level shifter and a control module electrically connected with an output of the level shifter. The control module is used for controlling an output signal of the level shifter to be a low level signal when each input clock signal for the level shifter is low.