Gate Driving Circuit Frequency Doubling for AMOLED Flicker Reduction
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Solution Overview
Problem
The existing gate driving circuits in Active-Matrix Organic Light-Emitting Diode (AMOLED) panels have limited frequency PWM signals, leading to flicker issues that can be recognized by the naked eye, resulting in poor display effects, especially when displaying high-frequency content like static two-dimensional codes.
Innovation Solution
A gate driving circuit with a frequency doubling control circuit and an effective output circuit, where shift registers are cascaded to provide a frequency doubling control signal after a preset time period, effectively doubling the frequency of the scanning signals output by the gate driving circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If PWM signal frequency is limited in gate driving circuit, then circuit complexity is reduced, but display quality deteriorates due to visible flicker
Solution Approach 1:
The gate driving circuit is segmented into multiple functional modules: a frequency doubling control circuit with cascaded second shift registers, and an effective output circuit with cascaded first shift registers. This segmentation allows the frequency doubling function to be isolated and implemented without redesigning the entire gate driving circuit, thus improving display quality while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
The frequency doubling control signal is generated in advance by the frequency doubling control circuit before being applied to the first shift register. The preset time period delay ensures that the frequency doubled signal is prepared beforehand, allowing the main output circuit to operate with higher frequency signals without requiring real-time complex processing, thereby improving display quality while keeping the circuit structure relatively simple.
2Reliability
If PWM signal frequency is increased to reduce flicker, then display quality is improved, but device complexity increases due to additional frequency doubling control circuit
Solution Approach 1:
The frequency doubling control circuit uses cascaded second shift registers that can serve dual purposes: generating frequency doubled control signals for PWM output, and potentially serving as part of the overall scanning signal generation system. This multi-functionality reduces the need for completely separate frequency doubling components, thereby improving display quality while minimizing the increase in device complexity.
Solution Approach 2:
The frequency doubling control circuit acts as an intermediary between the output control signal line and the first shift register. It receives the control signal, processes it through the cascade of second shift registers to double the frequency, and then feeds it to the first shift register. This intermediary approach allows frequency doubling to be implemented without directly modifying the main shift register structure, thus improving display quality while keeping the added complexity localized and manageable.
3Speed
If frequency doubling control circuit is added, then PWM signal frequency is doubled to eliminate flicker, but circuit complexity increases
Solution Approach 1:
The frequency doubling control circuit utilizes periodic clock signals fed into the cascaded second shift registers to generate the frequency doubled control signal. By leveraging the inherent periodic nature of clock signals and the sequential operation of shift registers, the circuit achieves frequency doubling through regular periodic actions rather than complex real-time processing, thus increasing signal frequency while keeping the circuit structure relatively simple and systematic.
Data Source
AI summary
Provided are a gate driving circuit, a display substrate, a display device and a gate driving method, the gate driving circuit includes: a frequency doubling control circuit and an effective output circuit including first shift registers, the first shift register at the first stage has a first signal input terminal coupled with an output control signal line and a second signal input terminal coupled with the frequency doubling control circuit; the frequency doubling control circuit is coupled to the output control signal line, for providing a frequency doubling control signal thereto after a preset time period from the receipt of the output control signal in response to an output control signal from the output control signal line; the first shift register at the first stage outputs a scanning signal in response to the output control signal and a scanning signal in response to the frequency doubling control signal.