Gate Driving Circuit Dynamic Voltage Regulation for Display Leakage

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Solution Overview

Problem

Current gate driving circuits for display devices are inadequate in accommodating different frame rates, particularly failing to efficiently manage leakage current and voltage regulation across varying update rates, such as 120 Hz and 60 Hz, which affects display quality and power consumption.

Innovation Solution

A gate driving circuit with serially coupled shift registers, incorporating a driving circuit, pull-up circuit, and auxiliary voltage regulator circuits that adjust voltage levels based on control signals to manage leakage current and voltage regulation, utilizing transistors and voltage regulator circuits to support different frame rates by switching between enable and disable levels for the control signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If the gate driving circuit operates at a higher frame rate (120 Hz), then the display quality is improved, but the leakage current increases and power consumption rises

Engineering Contradiction:
Improvedisplay qualityVSAvoidleakage current
Core Design Contradiction:
Illumination intensityVSLoss of energy

Solution Approach 1:

The patent implements dynamic voltage adjustment by switching between different voltage levels (first voltage level and second voltage level) based on the operating frame rate. The voltage regulator dynamically changes the voltage supplied to the shift register circuit according to whether it is operating at a higher or lower frame rate, thereby optimizing power consumption for each operating condition.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter of the shift register circuit based on the operating frame rate. By adjusting the voltage level according to the frame rate (120 Hz vs 60 Hz), the circuit optimizes the balance between display quality and power consumption, reducing leakage current when operating at lower frame rates.

Inventive Principle:
Principle #35Parameter changes

2Illumination intensity

If the gate driving circuit operates at a higher frame rate (120 Hz), then the display quality is improved, but the power consumption increases

Engineering Contradiction:
Improvedisplay qualityVSAvoidpower consumption
Core Design Contradiction:
Illumination intensityVSUse of energy by stationary object

Solution Approach 1:

The patent implements dynamic voltage adjustment by switching between different voltage levels (first voltage level and second voltage level) based on the operating frame rate. The voltage regulator dynamically changes the voltage supplied to the shift register circuit according to whether it is operating at a higher or lower frame rate, thereby optimizing power consumption for each operating condition.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter of the shift register circuit based on the operating frame rate. By adjusting the voltage level according to the frame rate (120 Hz vs 60 Hz), the circuit optimizes the balance between display quality and power consumption, reducing leakage current when operating at lower frame rates.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If the gate driving circuit operates at a lower frame rate (60 Hz), then the power consumption is reduced, but the display quality may deteriorate

Engineering Contradiction:
Improvepower consumptionVSAvoiddisplay quality
Core Design Contradiction:
Loss of energyVSIllumination intensity

Solution Approach 1:

The patent implements dynamic voltage adjustment by switching between different voltage levels (first voltage level and second voltage level) based on the operating frame rate. The voltage regulator dynamically changes the voltage supplied to the shift register circuit according to whether it is operating at a higher or lower frame rate, thereby optimizing power consumption for each operating condition.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter of the shift register circuit based on the operating frame rate. By adjusting the voltage level according to the frame rate (120 Hz vs 60 Hz), the circuit optimizes the balance between display quality and power consumption, reducing leakage current when operating at lower frame rates.

Inventive Principle:
Principle #35Parameter changes

4Illumination intensity

If the voltage is increased to maintain display quality at lower frame rates, then the display quality is maintained, but the leakage current increases

Engineering Contradiction:
Improvedisplay qualityVSAvoidleakage current
Core Design Contradiction:
Illumination intensityVSLoss of energy

Solution Approach 1:

The patent implements dynamic voltage adjustment by switching between different voltage levels (first voltage level and second voltage level) based on the operating frame rate. The voltage regulator dynamically changes the voltage supplied to the shift register circuit according to whether it is operating at a higher or lower frame rate, thereby optimizing power consumption for each operating condition.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter of the shift register circuit based on the operating frame rate. By adjusting the voltage level according to the frame rate (120 Hz vs 60 Hz), the circuit optimizes the balance between display quality and power consumption, reducing leakage current when operating at lower frame rates.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11120886B2Gate driving circuit and shift register controlling method
Publication Date: 2021.09.14 AU OPTRONICS CORP
  • US11120886B2 patent drawing
  • US11120886B2 patent drawing
  • US11120886B2 patent drawing

AI summary

A gate driving circuit comprises a plurality of shift registers coupled in serial. An nth shift register includes a driving circuit, a pull-up circuit and a first auxiliary voltage regulator circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a clock signal and output a gate signal according to the clock signal. The pull-up circuit is electrically coupled to the driving circuit. The first auxiliary voltage regulator circuit is electrically coupled to the pull-up circuit and a second node. The first auxiliary voltage regulator circuit is configured to receive a control signal and the second node corresponding to a second voltage.