Gate Driving Circuit Low-Frequency Driving Power Reduction

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Solution Overview

Problem

Display devices, particularly foldable and flexible displays, face limited usage time due to high power consumption, necessitating the development of methods to reduce power usage and extend battery life.

Innovation Solution

A gate driving circuit with multiple stages that includes input, output, and control parts to manage gate output signals, utilizing stabilizing and holding transistors to stabilize and maintain node signals, and a timing control unit to restrict unnecessary gate output signals in non-display regions, thereby reducing power consumption and enabling low-frequency driving.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If the gate driving circuit continuously outputs gate signals to all gate lines, then the display function is maintained, but power consumption increases

Engineering Contradiction:
Improvepower consumptionVSAvoidusage time
Core Design Contradiction:
Use of energy by stationary objectVSDuration of action of stationary object

Solution Approach 1:

The gate driving circuit implements low-frequency driving by periodically activating gate lines instead of continuous activation. The circuit includes a frequency control unit that generates clock signals at reduced frequencies, and a gate signal output unit that selectively activates gate lines at these lower frequencies, thereby reducing power consumption while maintaining display functionality during static image periods

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The circuit extracts and inactivates non-display region gate lines from the active driving cycle. The gate signal output unit selectively disables gate signals for regions that do not require display output, separating the necessary gate line activations from unnecessary ones, thereby reducing overall power consumption without affecting display quality in active regions

Inventive Principle:
Principle #2Taking out (Extraction)

2Use of energy by moving object

If the gate driving circuit inactivates non-display regions to reduce power consumption, then battery life is extended, but the complexity of signal control increases

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal control complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The circuit merges the functions of gate signal generation, frequency control, and region selection into an integrated gate driving circuit structure. The frequency control unit and gate signal output unit work as unified components, sharing common control logic and signal paths, which simplifies the overall control architecture while achieving both power reduction and selective region activation

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate driving circuit is designed with multi-functional units that can operate in different modes. The gate signal output unit can selectively switch between full-frequency driving for dynamic images and low-frequency driving for static images, providing universal functionality that adapts to different display requirements without requiring separate dedicated circuits for each mode

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9437168B2Gate driving circuit and display device including the same
Publication Date: 2016.09.06 SAMSUNG DISPLAY CO LTD
  • US9437168B2 patent drawing
  • US9437168B2 patent drawing
  • US9437168B2 patent drawing

AI summary

A gate driving circuit and display device including the same are disclosed. In one aspect, the gate driving circuit includes a plurality of stages, each stage including a first input portion configured to apply an input signal to a first node based on a first clock signal, a first output portion configured to output a second clock signal as a gate output signal based on a first node signal applied to the first node, a second input portion configured to apply the first clock signal to a second node based on the first node signal, a second output portion configured to output a first voltage as the gate output signal based on a second node signal applied to the second node, and an output control portion configured to activate the first output portion based on an output control signal.