Gate Driving Circuit High Frame Rate Multiplexer Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional display devices with multiplexer components face difficulties in operating at high frame rates due to limitations in switching capability, making them unsuitable for high frame rate display modes without significant changes in component configuration or design.
Innovation Solution
The proposed gate driving circuit employs a configuration of shift register circuits that receive and output drive signals based on specific clock signals, allowing for efficient operation in high frame rate modes without altering the original component configuration or design, by optimizing the timing of clock signals and enabling/disabling periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a multiplexer component is used to drive pixel rows, then the number of electronic components is reduced and cost is decreased, but the switching capability becomes insufficient for high frame rate operation
Solution Approach 1:
The gate driving circuit is divided into multiple shift register circuits (first, second, third, and fourth shift register circuits) that operate independently with different clock signals. This segmentation allows each circuit segment to handle specific timing requirements, enabling high frame rate operation while maintaining the multiplexer structure for cost efficiency.
Solution Approach 2:
The patent introduces dynamic clock signal timing control where each shift register circuit receives clock signals with different timing characteristics. The first clock signal has a first timing, the second clock signal has a second timing, and so on, allowing the system to dynamically adapt to high frame rate requirements while using the multiplexer component.
2Productivity
If the resolution ratio is increased to satisfy customer requirements, then more pixel rows need to be driven, but the electronic components and cost increase correspondingly
Solution Approach 1:
The multiplexer component is designed to serve multiple functions by being controlled by the multi-phase clock signals from the segmented shift register circuits. This allows a single multiplexer structure to handle increased pixel row driving requirements without proportionally increasing electronic components, maintaining cost effectiveness while supporting higher resolution ratios.
3Productivity
If the frame rate is increased to high frame rate mode, then the display performance is improved, but the switching capability of existing components becomes insufficient
Solution Approach 1:
The patent changes the timing parameters of clock signals to enable high frame rate operation. By introducing multiple clock signals with different timings (first timing, second timing, third timing, fourth timing) to different shift register circuits, the system achieves the necessary switching capability for high frame rates without changing the fundamental multiplexer component structure.
Data Source
AI summary
A gate driving circuit includes a plurality of shift register circuits, where the shift register circuits are configured to drive a plurality of pixel rows. The gate driving circuit may be operated in a first mode and a second mode. When the gate driving circuit is operated in the first mode, the gate driving circuit is configured to drive, in a single frame, all pixel rows to be displayed. When the gate driving circuit is operated in the second mode, the gate driving circuit is configured to drive, in the single frame, some of the pixel rows to be displayed, and driven pixel rows of two adjacent frames are different.