Gate Driving Circuit Narrow Frame Design
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Solution Overview
Problem
A large number of clock signal lines in gate driving circuits hinders the achievement of a narrow frame in display panels.
Innovation Solution
The gate driving circuit incorporates a plurality of cascaded gate driving units, where each unit includes a pull-up control module and a node signal control module that receives forward and reverse scan control signals to generate gate electrode driving signals without using clock signals, thereby reducing the number of clock signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional fan-out design with multiple clock signal lines is used, then the gate driving circuit can be implemented, but the frame size increases and narrow frame cannot be achieved
Solution Approach 1:
The patent extracts and eliminates the clock signal lines from the gate driving circuit by using a self-driven mechanism where the gate driving unit generates its own driving signals based on scan control signals, removing the need for external clock signal transmission lines
Solution Approach 2:
The gate driving unit is designed to perform multiple functions: it receives scan control signals, generates gate electrode driving signals, and controls the display panel scanning, eliminating the need for separate clock signal lines by integrating the clocking function into the scan control mechanism
2Area of stationary object
If multiple clock signal lines are used to transmit clock signals, then the gate driving circuit can operate, but more frames are needed to carry the circuit
Solution Approach 1:
The patent removes clock signal lines from the system by implementing a self-driven gate driving mechanism that uses scan control signals directly to generate gate electrode driving signals, eliminating the need for dedicated clock signal transmission infrastructure
3Length of moving object
If more thin film transistors are used in the node signal control module, then the circuit functionality is achieved, but the frame size increases
Solution Approach 1:
The patent merges the clock signal generation function with the scan control signal function, allowing the node signal control module to generate gate electrode driving signals using fewer transistors by utilizing the scan control signals directly rather than requiring separate clock signal processing circuits
Data Source
AI summary
A gate driving circuit and a display panel. The gate driving circuit includes a plurality of cascaded gate driving units, wherein a Nth stage gate driving unit includes a pull-up control module and a node signal control module. By an adjustment of the signals connected to a first input terminal, a second input terminal, a first control terminal, and a second control terminal of the node signal control module, an original driving time sequence can be realized without using a clock signal, which reduces a space occupied by a frame.