Gate Driving Circuit Reduces Clock Signals for Narrow LCD Frames
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Solution Overview
Problem
Conventional gate driving circuits in LCDs require numerous clock signal wires and transistors, making it difficult to design narrower frames and are restricted by manufacturing processes.
Innovation Solution
A gate driving circuit on an array substrate comprising an input module, a reset module, a latch module, and a signal processing module, which reduces the number of clock signals and transistors by generating transition signals and controlling transistor statuses using clock signals, allowing for efficient gate signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional gate driving circuit design is used, then the circuit can drive the gate electrodes, but the number of clock signal wires and transistors increases, making it unfavorable for narrower LCD frame design
Solution Approach 1:
The patent merges the functions of multiple clock signal wires into a single clock signal wire by using a shift register structure that sequentially transfers signals through multiple stages. Instead of requiring separate clock wires for each gate driving stage, the invention combines them into one shared clock signal path, thereby reducing the number of clock signal wires and transistors while maintaining the ability to drive all gate electrodes.
Solution Approach 2:
The gate driving circuit is divided into multiple sequential stages (first stage, second stage, third stage, etc.), where each stage drives a portion of the gate electrodes. The shift register segments the clock signal distribution, allowing each stage to be controlled sequentially through the same clock signal wire, thus reducing overall circuit complexity.
2Adaptability or versatility
If the line width of single stage GOA is reduced to form multiple stages of gate driving signals, then more gate stages can be formed, but the reduction of GOA circuits becomes extremely difficult due to process restrictions
Solution Approach 1:
Instead of reducing line width in the horizontal dimension to create more stages, the invention adds a temporal dimension by using sequential signal transfer through the shift register. Multiple gate driving stages are achieved by time-multiplexing the clock signal through sequential stages rather than spatial compression, avoiding the need to reduce line width below process limits.
Solution Approach 2:
The invention changes the operating parameters of the gate driving circuit by introducing a shift register mechanism that uses voltage level transitions (high voltage to low voltage) to control sequential stage activation. This parameter-based control allows multiple stages to be formed without compromising line width or encountering manufacturing process restrictions.
3Adaptability or versatility
If more clock signal wires and transistors are used in conventional GOA design, then more gate stages can be driven, but it is unfavorable to narrower LCD frame
Solution Approach 1:
The single clock signal wire in the invention serves multiple functions by sequentially controlling multiple gate driving stages through the shift register mechanism. Instead of requiring dedicated clock wires for each stage, one universal clock signal wire performs the function of distributing clock signals to all stages in sequence, thereby supporting multiple gate driving stages while maintaining a narrow frame.
Data Source
AI summary
A gate driving circuit disposed on an array substrate and an LCD using the same are described. The gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units. The gate driving circuit unit comprises an input module, a reset module, a latch module and a signal processing module. The signal processing module receives the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal. The present invention utilizes less clock signals and transistors, which is favorable to the narrower LCD's frame design and solves the problem of manufacturing process restriction of the LCD panel.