Gate Driving Circuit Node Controller for Scan Pulse Deviation
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Solution Overview
Problem
Existing gate driving circuits face challenges in minimizing output characteristic deviations between scan output buffer units, leading to suboptimal performance in display devices.
Innovation Solution
The proposed gate driving circuit incorporates a node controller to manage voltages of a first and second node based on set and reset signals, along with a carry pulse output unit and multiple scan pulse output units, where the carry clock transitions to a high level before and after the scan clocks, maintaining a high level state for specific periods to synchronize and stabilize the output pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shift register with multiple scan output buffer units is used to minimize circuit configuration, then device complexity is reduced, but output characteristic deviation between scan output buffer units increases
Solution Approach 1:
The node controller pre-charges or pre-discharges nodes before the scan output buffer units operate, ensuring that all units start from the same initial voltage state. This preliminary action compensates for inherent circuit variations and minimizes output characteristic deviation between parallel buffer units.
Solution Approach 2:
The node controller dynamically adjusts voltage levels and timing parameters for different nodes based on their position in the circuit. By changing voltage parameters adaptively, the system compensates for signal degradation and timing variations across multiple output buffer units.
2Productivity
If scan output buffer units operate simultaneously to improve productivity, then gate signal supply speed increases, but output characteristic uniformity deteriorates
Solution Approach 1:
Different nodes are assigned different voltage control characteristics tailored to their specific positions and loading conditions. The node controller applies localized voltage adjustments to each node, ensuring that despite simultaneous operation, all scan output buffer units produce uniform output characteristics adapted to their local requirements.
Data Source
AI summary
A gate driving circuit that minimizes output characteristic deviation between a plurality of scan output buffer units, and a display device comprising the gate driving circuit, are discussed. An Nth stage of the gate driving circuit, N being a natural number, can include a node controller configured to control voltages of a first node and a second node according to a set signal and a reset signal, a carry pulse output unit configured to receive a carry clock and output the carry clock as a carry pulse according to voltages of the first node and the second node, and a plurality of scan pulse output units configured to receive a plurality of scan clocks and output each of the scan clocks as a scan pulse according to voltages of the first node and the second node.