Gate Driving Circuit Node Precharging for Transistor Stress Reduction
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Solution Overview
Problem
Existing gate driving circuits in display devices face challenges in efficiently managing gate signals across multiple stages, leading to potential signal deterioration and reduced reliability due to prolonged gate voltage stress on transistors.
Innovation Solution
The proposed gate driving circuit incorporates a k-th stage with specific circuits: a first input circuit to precharge a node, a second input circuit to transmit signals from adjacent stages, an output circuit to generate gate signals, a first transfer circuit to transfer clock signals with a first time constant, and a second transfer circuit to discharge signals with a second time constant, minimizing duty ratio and stress on transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate signals are sequentially provided to multiple gate lines through multiple stages, then the display device can operate with proper timing control, but signal deterioration and transistor stress increase over time
Solution Approach 1:
The first node is precharged to a first voltage level before the gate signal is output, ensuring that the transistor is already in a ready state with minimal stress. This preliminary charging action occurs in advance through the first input circuit, reducing the duration of voltage stress during actual operation.
Solution Approach 2:
The gate driving circuit operates with periodic clock signals that rhythmically control the charging and discharging of nodes. This periodic action allows transistors to rest between operations, reducing cumulative stress while maintaining continuous display operation through the sequential stage structure.
2Reliability
If the gate driving circuit uses multiple transistors connected in sequence across stages, then signal transfer is achieved, but signal deterioration occurs
Solution Approach 1:
The first node and second node serve as intermediary elements between the input and output circuits. These intermediate nodes buffer and transfer signals with controlled voltage levels, preventing direct signal degradation through the transistor chain. The first transfer circuit acts as an intermediary to maintain signal integrity across stages.
Solution Approach 2:
The circuit dynamically changes voltage parameters at different nodes to optimize signal transfer. The first node transitions between first and second voltage levels, while the second node transitions between third and fourth voltage levels, ensuring that signals maintain proper levels throughout the multi-stage circuit and preventing deterioration.
3Reliability
If the gate driving circuit precharges nodes and transfers clock signals with specific time constants, then transistor stress is minimized, but circuit complexity increases
Solution Approach 1:
The gate driving circuit is segmented into distinct functional blocks: first input circuit, second input circuit, output circuit, first transfer circuit, and second transfer circuit. Each segment performs a specific function (precharging, signal transfer, discharging), which simplifies the design and analysis of each part while reducing overall transistor stress through specialized optimization.
Data Source
AI summary
A gate driving circuit includes a plurality of stages. A k-th stage from among the plurality of stages, the k-th stage includes a first input circuit to receive a (k−1)th gate signal from a (k−1)th stage and to precharge a first node, a second input circuit to receive a (k+2)th gate signal from a (k+2)th stage to transmit the received (k+2)th gate signal to a second node, an output circuit to output a first clock signal as a k-th gate signal in response to a signal of the first node, a discharge circuit configured to discharge the first node through the k-th gate signal in response to a signal of the second node, a first transfer circuit to transfer a second clock signal to the first node, and a second transfer circuit to transfer the first clock signal to the second node.