Gate Driving Circuit Noise Cancellation via Clock Edge Synchronization
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Solution Overview
Problem
Display devices experience noise generation due to clock signals, particularly at the rising and falling edges, which propagate through capacitance coupling to the gate lines and neighboring electrodes, affecting image quality and power consumption.
Innovation Solution
A gate driving circuit is designed with a control signal reception unit and a level shifting unit that generates clock signals with synchronized voltage rising and falling sections, each with different voltage levels, to minimize noise by pairing rising edges with falling edges of other clock signals, thereby canceling out noise at neighboring electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are supplied to gate lines, then gate driving signals are generated to control pixels, but noise is generated at rising and falling edges that propagates to neighboring electrodes through capacitance coupling
Solution Approach 1:
The patent applies preliminary anti-action by synchronizing the rising edge of one clock signal with the falling edge of another clock signal. This pre-planned synchronization creates opposing noise impulses that cancel each other out before they can propagate to neighboring electrodes through capacitance coupling, thereby preventing noise generation while maintaining gate driving signal functionality
Solution Approach 2:
The patent converts the harmful noise generated at clock signal edges into a beneficial effect by deliberately synchronizing rising and falling edges. The noise that would normally be harmful is transformed into a useful cancellation mechanism, where the harmful electromagnetic interference from one clock signal's edge is neutralized by the opposing edge of another clock signal, improving overall system reliability
2Object-affected harmful factors
If voltage levels of clock signals are changed, then noise propagation is reduced, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by synchronizing the timing of voltage transitions (rising and falling edges) rather than changing voltage levels. This temporal parameter adjustment reduces noise propagation through capacitance coupling without requiring increased power consumption, as the solution operates within the existing voltage parameters while optimizing their temporal arrangement
3Object-generated harmful factors
If multiple clock signals are synchronized, then noise is canceled at neighboring electrodes, but circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the clock signal generation into distinct phases and channels, where each clock signal is independently controlled and synchronized. This segmentation allows for systematic noise cancellation through edge synchronization while maintaining manageable circuit complexity through modular signal generation and control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise propagation, improves power efficiency, and minimizes heat generation and power consumption by synchronizing voltage sections of clock signals, leading to enhanced image quality and reduced noise in display devices.
Implementation Method 1
A gate line to which the gate driving signal is supplied is coupled to electrodes disposed on the display panel or peripheral circuits, by capacitance or the like. Through the coupling, the rising edge and the falling edge of the clock signal may propagate to the display panel or the peripheral circuit while generating noise.
Data Source
AI summary
The present invention attenuates noise appearing at neighboring electrodes by causing a rising edge of one clock signal to be synchronized with a falling edge of another one clock signal when a clock signal for gate driving is generated.