Gate Driving Circuit for Display Devices with Overlap Timing Control
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Solution Overview
Problem
Existing display devices suffer from deteriorated image quality due to insufficient charging in subpixels, leading to issues like image blurriness and brightness variations between subpixel lines, which are not effectively addressed by current technologies.
Innovation Solution
The implementation of a gate driving circuit and driving method that improves charging rates through overlap driving and fake data insertion driving, with advanced overlap driving techniques that control the timing of gate signals to prevent image abnormalities and enhance charging efficiency by adjusting the channel width-to-length ratio of sense transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If overlap driving is applied to improve charging rate, then image quality improves, but device complexity increases due to additional gate signal control requirements
Solution Approach 1:
The gate driving circuit is divided into separate scan clock signal generator and sense clock signal generator modules, each independently generating clock signals for different transistor groups. This segmentation allows overlap driving to be implemented without significantly increasing overall circuit complexity, as each module handles a specific function.
Solution Approach 2:
The scan clock signal and sense clock signal are generated with predetermined timing relationships and phase differences before being applied to the transistors. This preliminary timing arrangement enables overlap driving to improve charging rates without requiring complex real-time control logic during operation.
2Reliability
If fake data insertion driving is used to prevent image blurriness, then image distinctness improves, but charging time is reduced
Solution Approach 1:
The channel width-to-length ratio of the sense transistor is optimized to compensate for reduced charging time caused by fake data insertion. By adjusting this physical parameter, the transistor's conductance is increased to maintain adequate charging within the shortened time window, thus preserving image quality without requiring extended charging periods.
3Reliability
If advanced overlap driving with delayed sense signal is implemented, then image abnormalities are prevented, but device complexity increases due to additional delay control mechanisms
Solution Approach 1:
The sense clock signal is generated with a periodic phase delay relative to the scan clock signal. This regular timing pattern ensures that the sense transistor operates during the appropriate overlap period without requiring complex adaptive control, thereby preventing image abnormalities while maintaining relatively simple circuit architecture.
4Productivity
If sense transistor channel width-to-length ratio is increased to compensate for reduced charging time, then charging efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The channel width-to-length ratio of the sense transistor is optimized to compensate for reduced charging time caused by fake data insertion. By adjusting this physical parameter, the transistor's conductance is increased to maintain adequate charging within the shortened time window, thus preserving image quality without requiring extended charging periods.
Data Source
AI summary
The present invention relates to a display device, a gate driving circuit, and a driving method thereof, and more specifically, to a display device, a gate driving circuit, and a driving method thereof capable of solving problems with insufficient charging time or image abnormalities by controlling supply timing of two gate signals, e.g., scan signals and sense signals.