Gate Driving Circuit Polarity Control for Display Substrates
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Solution Overview
Problem
Existing gate driving circuits in liquid crystal display panels face challenges in achieving fast charging of pixel units while maintaining display quality, especially in high-resolution displays, due to issues with signal polarity inversion in dot inversion driving modes, which can result in reverse pre-charging and adverse display effects.
Innovation Solution
A gate driving circuit with a series connection of shift register units, where each stage outputs a second effective signal for pre-charging and a first effective signal for data writing, ensuring the same polarity distribution for pre-charging and data signals, thereby reducing reverse pre-charging and improving writing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the output time of each shift register unit exceeds the turn-on time of pixel units with overlap between different rows, then fast charging of pixel units is achieved, but reverse pre-charging occurs in dot inversion driving mode causing adverse display effects
Solution Approach 1:
The patent applies preliminary action by introducing a start shift register unit that outputs a start signal before the main driving shift register unit outputs the scan signal. This start signal pre-charges the pixel units with the correct polarity in advance, ensuring that when the scan signal arrives, the pixel units are already in the correct charging state without experiencing reverse pre-charging. The timing is arranged so that the start signal is output earlier than the scan signal, achieving fast charging while maintaining display quality.
2Speed
If multiple shift register units output signals with time overlap to achieve fast charging, then writing speed improves, but polarity distribution becomes inconsistent causing display defects
Solution Approach 1:
The patent segments the signal output function into two distinct parts: a start shift register unit that outputs the start signal for pre-charging, and a driving shift register unit that outputs the scan signal for data writing. This segmentation ensures that the pre-charging phase and data writing phase are separated in time and function, allowing each phase to maintain consistent polarity distribution without interference, while still achieving fast overall operation through the overlapping timing arrangement.
Data Source
AI summary
The present invention is related to a gate driving circuit for a display device. The gate driving circuit may comprise x stages of driving shift register units connected in series. Each of the driving shift register units may comprise an input terminal, an output terminal, and a reset terminal. The input terminal may comprise a first input port and a second input port. A row of pixel units driven by the driving shift register unit of the m-th stage may have the same polarity distribution as a row of pixel units driven by the driving shift register unit of the (m−N)-th stage. N is an integer greater than 1. m is an integer and N+1<m≤x.