Gate Driving Circuit with Pre-Charging for Display Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As display device resolutions increase, there is a challenge in maintaining consistent pixel charging times and reducing variations in charging rates between upper and lower end pixels, leading to potential defects in display quality.
Innovation Solution
A gate driving circuit with cascaded stages, including a first output unit, a control unit, a pull-down unit, a holding unit, and a stabilization unit, which generate and control gate signals with specific voltage levels to ensure uniform charging across the display panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the resolution of the display device is increased, then the display quality is improved, but the pixel charging time becomes insufficient and charging rate variation increases
Solution Approach 1:
The patent applies preliminary action by providing a first low voltage to the gate output terminal before the gate on voltage is outputted. This pre-charging or pre-conditioning of the gate line reduces the time required for pixel charging when the resolution is increased, thereby maintaining sufficient charging time despite the higher resolution requirement.
2Manufacturing precision
If the resolution of the display device is increased, then the display quality is improved, but the variation in charging rates between upper end pixels and lower end pixels increases
Solution Approach 1:
The patent applies preliminary action by providing a first low voltage to the gate output terminal before the gate on voltage is outputted. This pre-conditioning reduces the variation in charging rates between upper end pixels and lower end pixels, ensuring more uniform charging across the display panel even at higher resolutions.
Solution Approach 2:
The patent applies local quality by using different voltage levels at different stages of the gate signal output. Specifically, a first low voltage is provided before the gate on voltage, and a second low voltage (higher than the first) is provided after the gate on voltage. This localized voltage adjustment compensates for the voltage drop along the gate lines, ensuring uniform charging rates across different regions of the display panel.
3Device complexity
If a simple gate driving circuit is used, then the device complexity is reduced, but the pixel charging time becomes insufficient
Solution Approach 1:
The patent applies preliminary action by adding a first pull-down unit and a first holding unit to the gate driving circuit. These units provide a first low voltage to the gate output terminal before the gate on voltage is outputted, which prepares the gate line for faster charging. This preliminary action ensures sufficient pixel charging time without requiring a completely complex gate driving circuit design.
Solution Approach 2:
The patent applies parameter changes by introducing multiple voltage levels in the gate signal output process. A first low voltage is provided before the gate on voltage, and a second low voltage (higher than the first) is provided after the gate on voltage. This parameter change optimizes the charging time by creating a more favorable voltage profile for pixel charging, achieving sufficient charging time with a relatively simple circuit modification.
4Device complexity
If voltage is provided only after gate on voltage is outputted, then the circuit is simplified, but the pixel charging time is insufficient and charging rate variation is high
Solution Approach 1:
The patent applies preliminary action by providing a first low voltage to the gate output terminal before the gate on voltage is outputted. This pre-conditioning of the gate line is essential for achieving sufficient pixel charging time and reducing charging rate variation. By adding this preliminary voltage provision step, the circuit maintains relative simplicity while significantly improving the charging performance.
Data Source
AI summary
A gate driving circuit including a plurality of stages to respectively output gate signals to gate lines and connected to each other in cascade, an ith stage from among the plurality of stages including: a first output unit to generate a gate signal from a clock signal received at an input terminal; a first control unit to control the potential of a first node; a first pull-down unit to provide a first low voltage to a gate output terminal to drop down the gate signal, the first low voltage being lower than a gate off voltage of the gate signal; a first holding unit and a stabilization unit, each to provide a second low voltage having a higher level than that of the first low voltage to the gate output terminal; and a second control unit to control an operation of the first holding unit.