Gate Driving Circuit Shared Pull-Down Control Sub-Circuit
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Solution Overview
Problem
Conventional gate driving circuits require a large number of transistors, leading to increased bezel area and high power consumption due to the need for multiple pull-down control sub-circuits in each shift register unit.
Innovation Solution
A gate driving circuit design where multiple shift register units are grouped into stages, with each group sharing a single pull-down control sub-circuit connected to a high-voltage port, a pull-down node, and a low-voltage port, reducing the total number of pull-down control sub-circuits and transistors, thereby minimizing bezel area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple pull-down control sub-circuits are used in each shift register unit, then the gate driving circuit can drive more gate lines, but the number of transistors increases leading to larger bezel area and higher power consumption
Solution Approach 1:
Multiple pull-down control sub-circuits are merged into a single shared sub-circuit that serves multiple shift register units. The pull-down control sub-circuit is configured to receive clock signals and generate pull-down signals that are shared across N shift register units, reducing the total transistor count while maintaining the ability to drive multiple gate lines sequentially
Solution Approach 2:
The single pull-down control sub-circuit is designed to perform multiple functions by sequentially controlling different shift register units. It receives a single clock signal and generates pull-down signals for multiple gate lines through time-multiplexed operation, making one sub-circuit serve the role of multiple sub-circuits
2Reliability
If multiple pull-down control sub-circuits are used in each shift register unit, then each unit can be independently controlled, but power consumption increases due to the larger number of active transistors
Solution Approach 1:
Multiple independent pull-down control sub-circuits are merged into a single shared sub-circuit that maintains independent control capability through sequential operation. The sub-circuit is controlled by a clock signal that enables it to switch between controlling different shift register units, reducing power consumption by having fewer transistors in active states simultaneously
3Productivity
If multiple pull-down control sub-circuits are used in each shift register unit, then the circuit can handle more gate lines, but the bezel area increases due to more transistors
Solution Approach 1:
Multiple pull-down control sub-circuits are merged into a single shared sub-circuit that controls multiple shift register units. This merging reduces the total number of transistors required, thereby reducing the bezel area occupied by the gate driving circuit while maintaining the capability to drive a large number of gate lines through sequential scanning
Solution Approach 2:
The circuit transitions from a spatial arrangement where each shift register unit has its own pull-down control sub-circuit to a time-multiplexed arrangement where a single sub-circuit serves multiple units sequentially. This dimensional change from space to time allows the same functional capability with reduced physical footprint
Data Source
AI summary
The present application discloses a gate driving circuit having multiple shift register units cascaded one after another in multiple stages. The multiple shift register units are grouped into a plurality of groups of shift register units, each of the plurality of groups of shift register units having a plurality of shift register units. Each of the plurality of groups of shift register units includes a single pull-down control sub-circuit.