Gate Driving Circuit with Opposite-Side Pull-Up Transistors
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Solution Overview
Problem
Existing liquid crystal display panel designs face challenges in balancing area utilization with driving capability, particularly in narrow-border displays where efficient gate driving is necessary without excessive circuit area increase.
Innovation Solution
The implementation of a gate driving circuit with staggered and single-drive shift registers, where pull-up transistors are disposed on opposite sides of the pixel array, enhancing driving capability while maintaining a compact circuit architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If shift registers are placed on both sides of the pixel array to enhance driving capability, then the driving capability is improved, but the circuit area increases
Solution Approach 1:
The patent combines the functions of pull-up transistors from both sides into a shared configuration. The pull-up transistors on opposite sides are coupled to receive the same clock signal, allowing them to work cooperatively to drive the same gate line, thereby enhancing driving capability while avoiding duplication of full circuit structures
Solution Approach 2:
The pull-up transistors are designed to serve multiple functions: they receive clock signals from either side's shift registers, drive gate lines collectively, and can operate in coordination with transistors from both left and right shift register chains, maximizing resource utilization
2Power
If pull-up transistors are added to enhance driving capability, then the driving capability is improved, but the device complexity increases
Solution Approach 1:
The patent applies pull-up transistors selectively at specific locations (opposite sides of the pixel array) rather than uniformly across the entire circuit. This localized approach enhances driving capability where most needed while minimizing unnecessary complexity in other regions
Solution Approach 2:
The configuration allows asymmetric placement of pull-up transistors on opposite sides with different coupling arrangements, enabling flexible adaptation to different driving requirements while maintaining overall circuit simplicity through the shared clock signal reception mechanism
Data Source
AI summary
Provided is a gate driving circuit, coupled to a pixel array having multiple gate lines. The gate driving circuit includes multiple shift registers and multiple pull-up transistor, coupled to the pixel array and separately located on two opposite sides of the pixel array. Shift registers located on a same side are sequentially coupled to each other. An nth (n is a positive integer) pull-up transistor includes: a control end, coupled to a control end of a driving transistor of an (n−1)th shift register located on a same side as the nth pull-up transistor; a first end, used to receive a clock signal, where the clock signal is further input to an nth shift register of the shift registers located on an opposite side of the nth pull-up transistor; and a second end, coupled to an nth gate line of the pixel array and used to drive the nth gate line.