Gate Driving Circuit Reduces Pulse Signal Inputs for High-Resolution Displays
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Solution Overview
Problem
The high cost and increased complexity of manufacturing high-resolution display panels due to the need for multiple gate driving circuit chips, along with the risk of short circuits and defects from densely arranged wires on the fan-out area.
Innovation Solution
A gate driving circuit with multiple gate driving units, each connected to a pulse signal input end and at least two adjacent gate scanning lines, controlled by a timing control signal, allowing for reduced pulse signal input ends and a more efficient distribution of pulse signals, thereby reducing the number of gate driving circuits and the likelihood of defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of gate scanning lines is increased to achieve high resolution, then the display quality is improved, but the number of gate driving circuit chips is increased, leading to increased manufacturing cost
Solution Approach 1:
The patent combines the functions of multiple gate driving circuit chips into a single integrated gate driving circuit. The circuit uses a scanning signal input end connected to a scanning signal generator and multiple gate scanning lines connected to pixel circuits, allowing one chip to drive multiple gate scanning lines through shared control structures and signal distribution networks, thereby reducing the total number of chips needed for high-resolution displays.
2Measurement precision
If the number of gate scanning lines is increased, then the display resolution is improved, but the number of pulse signal input ends is increased, leading to increased manufacturing cost
Solution Approach 1:
The patent implements a multi-functional pulse signal input structure where a single scanning signal input end can control multiple gate scanning lines through time-division multiplexing and shared control logic. The scanning signal generator produces scanning signals that are distributed to multiple gate scanning lines, allowing one input end to serve multiple functions and reduce the total number of input ends required.
3Area of stationary object
If wires on the fan-out area are arranged closely to reduce space, then the space utilization is improved, but the risk of short circuit or open circuit is increased
Solution Approach 1:
The patent addresses the wire routing problem by transitioning from a two-dimensional planar arrangement to a three-dimensional layered structure. Multiple wire layers are stacked vertically with appropriate spacing, allowing wires to be routed in different dimensions. This reduces the horizontal density of wires on the fan-out area while maintaining reliable connections, as wires in different layers can be positioned closer without risking short circuits between them.
Data Source
AI summary
A gate driving circuit according to the present disclosure may include: a plurality of gate driving units, each of which is connected to a pulse signal input end, a timing control signal input end and at least two adjacent gate scanning lines respectively, and configured to sequentially provide the at least two adjacent gate scanning lines connected thereto with a pulse signal inputted by the pulse signal input end under a control of a timing control signal inputted by the timing control signal input end. The pulse signal input end is connected to a gate driver which outputs the pulse signal based on a number of gate scanning lines corresponding to each of the gate driving units.