Gate Driving Circuit Clock Racing Prevention
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Solution Overview
Problem
Existing gate driving circuits face reliability issues due to clock racing effects and transistor deterioration, particularly in long-time driving or high-temperature environments, which affect the stability and efficiency of gate signal transmission.
Innovation Solution
The proposed gate driving circuit incorporates a cascade-connected structure with a discharge circuit and carry feedback circuit, utilizing multiple clock signals and voltage levels to manage carry signals effectively, reducing clock racing effects and transistor stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional shift register structure is used for gate driving, then the circuit can operate with simple structure, but clock racing effects occur and transistor deterioration happens under long-time driving or high-temperature conditions
Solution Approach 1:
The gate driving circuit is divided into multiple independently controllable driving stages, each with its own discharge transistor and carry feedback mechanism. This segmentation allows each stage to be optimized and controlled separately, preventing cascading failures and reducing the impact of transistor deterioration in any single stage.
Solution Approach 2:
The discharge transistor is activated in advance to discharge the carry signal before the clock racing effect can propagate through subsequent stages. By performing this discharge action preliminarily, the circuit prevents the accumulation of harmful effects that would otherwise occur during long-time driving or high-temperature operation.
2Productivity
If multiple driving stages are cascade-connected to sequentially provide gate signals, then gate signal transmission can be achieved, but clock racing effects occur causing reliability issues
Solution Approach 1:
A carry feedback circuit is implemented that feeds back the discharge status of each driving stage to control the timing of subsequent stages. This feedback mechanism ensures that each stage completes its operation and discharges its carry signal before the next stage is activated, eliminating clock racing effects while maintaining efficient sequential gate signal transmission.
Solution Approach 2:
The discharge transistor is designed to activate before potential clock racing effects can occur, applying a counter-action that prevents the harmful effects from developing. This preliminary anti-action disrupts the clock racing effect at its source, protecting the cascade-connected stages from reliability degradation.
3Duration of action of moving object
If transistors operate continuously in cascade-connected driving stages, then gate signals can be sequentially output, but transistor deterioration occurs particularly in long-time driving or high-temperature environments
Solution Approach 1:
Each driving stage incorporates periodic discharge cycles where the discharge transistor is activated at regular intervals to reset the carry signal. This periodic action prevents continuous stress accumulation in the transistors, allowing the circuit to operate indefinitely without performance degradation even in high-temperature environments.
Solution Approach 2:
The discharge transistor periodically discards accumulated charge in the carry signal path, resetting the stage to a fresh state. This discarding and recovering mechanism prevents continuous operation from causing transistor deterioration, as each stage is regularly refreshed and prevented from entering a degraded state.
Data Source
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AI summary
A gate driving circuit includes: a plurality of stages, a k-th stage from among the plurality of stages, the k-th stage including: an input circuit to receive a previous carry signal and to pre-charge a first node; a first output circuit to output a k-th gate signal; a second output circuit to output a k-th carry signal; a discharge hold circuit to transmit a clock signal to a second node, and to discharge the second node with a second low voltage; a first pull down circuit to discharge the k-th gate signal with a first low voltage, and to discharge the first node and the k-th carry signal with the second low voltage; and a discharge circuit for discharging the k-th carry signal with the second low voltage in response to the previous carry signal.