Gate Driving Circuit Resistor Compensation for Display Fine Lines

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Solution Overview

Problem

In liquid crystal display technology, the low pixel charging rate due to voltage being pulled down in gate driving circuits leads to the horizontal fine line phenomenon, where periodic horizontal fine lines appear on the display panel, affecting image quality.

Innovation Solution

A gate driving circuit design with cascaded shift register units, where the second clock signal line is connected to a resistor with a higher resistance value than the first, increasing the falling time of the signal and charging time of pixels, thereby compensating for the low pixel charging rate and reducing or eliminating the horizontal fine line phenomenon.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If the second clock signal line is connected to a resistor with higher resistance value, then the falling time of the signal is increased and pixel charging time is extended, but the circuit complexity increases

Engineering Contradiction:
Improvepixel charging timeVSAvoidcircuit complexity
Core Design Contradiction:
Duration of action of moving objectVSDevice complexity

Solution Approach 1:

The patent applies different resistance values to different clock signal lines specifically at positions where voltage pulling down occurs. The second clock signal line is connected to a resistor with higher resistance value than the first clock signal line, creating localized compensation rather than uniformly changing the entire circuit. This targeted approach extends pixel charging time for affected rows without unnecessarily complicating the entire gate driving circuit.

Inventive Principle:
Principle #3Local quality

2Reliability

If the resistance value of the second resistor is increased to compensate for voltage pulling down, then the horizontal fine line phenomenon is reduced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvedisplay uniformityVSAvoidresistance value control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the resistance value parameter of the second resistor to be higher than that of the first resistor. This parameter adjustment compensates for the voltage pulling down effect on the second clock signal line, thereby reducing the horizontal fine line phenomenon and improving display uniformity across different pixel rows.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed gate driving circuit effectively increases the charging time of pixels, improving image quality by reducing or eliminating the horizontal fine line phenomenon, ensuring uniform brightness across rows.

Implementation Method 1

by connecting the second resistor to the second clock signal line, the gate driving circuit can increase the falling time Tf of the signal on the second clock signal line

Methodology Applied
Scientific EffectRC time constant: Capacitance

Data Source

PatentUS11705085B2Gate driving circuit and display panel
Publication Date: 2023.07.18 WUHAN BOE OPTOELECTRONICS TECH CO LTD
  • US11705085B2 patent drawing
  • US11705085B2 patent drawing
  • US11705085B2 patent drawing

AI summary

A gate driving circuit and a display panel are provided. The gate driving circuit includes a plurality of shift register units as cascaded, and the plurality of shift register units as cascaded includes a first shift register unit including a first clock signal terminal, an (n+1)-th shift register unit including an (n+1)-th clock signal terminal, a second shift register unit including a second clock signal terminal, and an (n+2)-th shift register unit including an (n+2)-th clock signal terminal. The gate driving circuit further includes a first clock signal line connected to the first clock signal terminal and the (n+1)-th clock signal terminal, and a second clock signal line connected to the second clock signal terminal and the (n+2)-th clock signal terminal.