Gate Driving Circuit Ripple Reduction and TFT Stress Management
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Solution Overview
Problem
Existing gate driving circuits for display devices face challenges in reducing ripples in gate signals without increasing the bezel area, particularly when driving landscape panels, and suffer from TFT degradation due to DC stress and increased TFT size requirements.
Innovation Solution
A gate driving circuit with a Q node controller, QB node controller, and output unit that alternates QB node voltage and uses smaller TFTs to minimize ripples and prevent DC stress, allowing for a more compact design by reducing TFT size and number.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a GIP circuit includes a pull-down TFT for maintaining stable low level of gate signal, then gate signal stability is improved, but the number of TFTs increases and TFT size must be enlarged
Solution Approach 1:
The patent combines the pull-up TFT and pull-down TFT into a single integrated switch circuit unit within each stage of the shift register. This merging approach maintains the stable low level capability provided by the pull-down TFT while organizing the circuit in a compact cascade structure, thereby achieving gate signal stability without proportionally increasing overall device complexity.
2Reliability
If TFT size is enlarged to cope with threshold voltage increase due to DC stress degradation, then reliability is improved, but bezel area increases
Solution Approach 1:
The patent implements periodic switching of the QB node voltage between high and low levels during non-scan periods. This periodic action prevents continuous DC stress on the pull-down TFT by alternately reversing the stress polarity, thereby maintaining TFT reliability and preventing threshold voltage degradation without requiring enlarged TFT sizes that would increase bezel area.
3Stability of the object's composition
If pull-down TFT is added to maintain QB node at high level, then gate signal low level stability is improved, but TFT degradation due to DC stress increases
Solution Approach 1:
The patent employs periodic reversal of the QB node voltage state during non-scan periods, alternating between high and low levels. This periodic action ensures that the pull-down TFT does not remain continuously stressed in one direction, thereby maintaining its ability to stabilize the gate signal low level while preventing cumulative DC stress degradation of the TFT.
4Device complexity
If simple GIP circuit with only pull-up TFT is employed, then device complexity is reduced, but ripples occur in gate signals when driving landscape panels
Solution Approach 1:
The patent merges the pull-up and pull-down TFTs into an integrated switch circuit within each shift register stage, creating a compact design that maintains circuit simplicity while eliminating gate signal ripples. The combined structure allows coordinated operation of both TFTs to maintain stable gate signal levels without the complexity of separate control circuits.
Solution Approach 2:
The patent introduces dynamic control of the QB node voltage that switches between high and low states during non-scan periods. This dynamic adjustment enables the circuit to actively counteract ripple conditions that would occur with a static pull-up only design, thereby maintaining gate signal stability while preserving relative circuit simplicity through coordinated TFT operation.
Data Source
AI summary
The present disclosure relates to a gate driving circuit and a display device using the circuit. A gate driving circuit according to an aspect of the present disclosure comprises a Q node controller, a QB node controller, and an output unit generating a pulse-type output signal by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node, and the QB node controller controls the voltage of the QB node in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.