Gate Driving Circuit Segmentation for Display Bezel Reduction
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Solution Overview
Problem
Existing display apparatuses face challenges with increased bezel area and gate pulse delay due to the placement of shift registers in bezel areas, which affect the design and performance, especially in large display panels and high-speed driving applications.
Innovation Solution
The display apparatus incorporates gate driving circuits in non-display areas on three sides, excluding the pad part, to reduce bezel areas and prevent gate pulse delay, with specific circuits in second to fourth non-display areas to manage gate line groups efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the shift register is disposed in the left and right bezel areas using a double feeding method, then the gate pulse can be supplied to the gate lines, but the design area of the shift register increases the left bezel area and the right bezel area
Solution Approach 1:
The gate driving function is segmented into three separate gate driving circuits disposed in different non-display areas (second, third, and fourth non-display areas). Each circuit drives specific gate line groups, distributing the functionality across multiple locations rather than concentrating it in the bezel areas, thereby reducing the required bezel area while maintaining gate pulse supply capability.
Solution Approach 2:
The patent transitions from a horizontal distribution approach (double feeding in left and right bezel areas) to a multi-dimensional distribution by utilizing non-display areas on multiple sides (second, third, and fourth non-display areas). This spatial reconfiguration reduces the horizontal bezel area requirement while achieving comprehensive gate line coverage through vertical and lateral distribution.
2Area of stationary object
If the interlacing method is applied to a large display panel, then the gate pulse can reach across the panel, but the delay of the gate pulse increases as the distance from the input terminal increases
Solution Approach 1:
The gate line groups are segmented and assigned to different gate driving circuits based on their spatial locations. Each gate driving circuit is positioned near the gate lines it serves, creating localized driving zones. This segmentation reduces the distance gate pulses must travel from the input terminal to the gate lines, thereby minimizing delay across large display panels.
Solution Approach 2:
Each gate driving circuit is strategically positioned in specific non-display areas (second, third, and fourth non-display areas) to provide localized gate pulse generation and distribution. This local quality approach ensures that each region of the display panel receives gate pulses from a nearby source, reducing propagation delay compared to a centralized input terminal approach.
3Speed
If multiple gate driving circuits are disposed in different non-display areas, then the bezel areas are reduced and gate pulse delay is prevented, but the device complexity increases
Solution Approach 1:
The three gate driving circuits perform identical gate driving functions but are distributed to different spatial locations and assigned to different gate line groups. This universality allows each circuit to operate independently with the same functional design, simplifying the overall system architecture despite the increased number of components, as each unit can be designed and manufactured using the same standardized approach.
Data Source
AI summary
Disclosed is a display apparatus. The display apparatus includes a substrate including a first substrate, including pixels connected to a plurality of gate lines, and first to fourth non-display areas surrounding the display area, a first gate driving circuit disposed in the second non-display area to drive a first gate line group among the plurality of gate lines, a second gate driving circuit disposed in the third non-display area to drive a second gate line group among the plurality of gate lines, and a third gate driving circuit disposed in the fourth non-display area to drive the first and second gate line groups.