Gate Driving Circuit Segmentation for Display Panel Refresh Rate
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Solution Overview
Problem
High-end display products with 8K resolution and 120 Hz refresh rate face challenges in maintaining image quality due to the short charging duration of pixel rows, which is affected by delays in gate scanning and data signals, leading to cross-row problems and reduced CM value.
Innovation Solution
A display panel with a gate driving circuit comprising shift registers arranged in sequence, combined into N groups of gate driving sub-circuits, where odd-numbered and even-numbered groups are alternately enabled to provide gate scanning signals, effectively managing clock and trigger signals to synchronize data signal writing with pixel charging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate scanning and data signals are transmitted sequentially to pixel rows, then the display panel can operate at high refresh rates, but the charging duration of pixel rows becomes too short, causing cross-row problems and reduced CM value
Solution Approach 1:
The gate driving circuit is divided into multiple independent driving units, each responsible for driving specific pixel rows. This segmentation allows parallel charging of multiple pixel rows simultaneously, effectively increasing the charging duration without reducing the refresh rate. Each driving unit can independently control its assigned rows, enabling overlapping operations that resolve the time conflict between scanning and charging.
2Device complexity
If a single gate driving circuit drives all pixel rows sequentially, then the device complexity is low, but the gate scanning delay causes cross-row problems and poor image quality
Solution Approach 1:
The gate driving circuit is divided into multiple independent driving units, each responsible for driving specific pixel rows. This segmentation allows parallel charging of multiple pixel rows simultaneously, effectively increasing the charging duration without reducing the refresh rate. Each driving unit can independently control its assigned rows, enabling overlapping operations that resolve the time conflict between scanning and charging.
3Manufacturing precision
If the charging duration of pixel rows is extended, then cross-row problems can be avoided, but the gate scanning and data signal transmission time increases, reducing the refresh rate
Solution Approach 1:
Multiple pixel rows are pre-selected and prepared for parallel charging before the gate scanning sequence begins. The driving units are pre-configured to charge their assigned rows simultaneously as the scanning progresses, rather than waiting for sequential completion. This preliminary preparation enables overlapping of scanning and charging operations, maintaining high refresh rates while ensuring sufficient charging time for all rows.
Data Source
AI summary
A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits includes a shift register of an m-th stage and a shift register of an (m+L*N)-th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N.