Gate Driving Circuit Shift Register Pull-Down TFT Reliability
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Solution Overview
Problem
The reliability of gate driving circuits in display devices is compromised due to the deterioration of thin film transistors, particularly the pull-down TFTs, which are subjected to excessive stress and abnormal operation, leading to reduced reliability and performance.
Innovation Solution
The introduction of resistors in series between the output node and the low-level power voltage substitutes the pull-down TFT, reducing the turn-on time of the ninth TFT and improving the reliability of the shift register by omitting the pull-down TFT, thereby stabilizing the gate voltage output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pull-down TFT is used in the shift register stage, then the gate voltage can be pulled down to low level, but the TFT deteriorates due to excessive stress and abnormal operation reducing reliability
Solution Approach 1:
The patent extracts and removes the pull-down TFT from the shift register stage circuit. By taking out the problematic pull-down TFT component, the source of deterioration and abnormal operation is eliminated, thereby improving the reliability of the shift register without the harmful effects of TFT stress and degradation
Solution Approach 2:
The patent replaces the durable but stress-prone pull-down TFT with resistors that can handle the pull-down function without deteriorating. The resistors serve as a more reliable, maintenance-free alternative that doesn't suffer from the same degradation mechanisms as TFTs under continuous stress
2Reliability
If the ninth TFT turn-on time is reduced, then the reliability of the shift register is improved, but the gate voltage stability may be affected
Solution Approach 1:
The patent introduces resistors as intermediary components between the ninth TFT and the low-level power voltage. These resistors mediate the pull-down function, allowing the ninth TFT to have reduced turn-on time while the resistors ensure stable gate voltage by providing controlled current paths and preventing voltage fluctuations
3Reliability
If the pull-down TFT is omitted, then the reliability is improved by preventing abnormal operations, but additional resistors must be added to the circuit
Solution Approach 1:
The patent merges the pull-down function with the existing resistor network in the circuit. By combining the pull-down capability into the resistor configuration rather than using a separate pull-down TFT, the circuit achieves improved reliability while minimizing the increase in device complexity through functional integration
Data Source
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AI summary
A gate driving circuit (140) sequentially outputting a gate voltage using a high level power voltage (VDD), a low level power voltage (VSS), a start voltage (VST), a previous stage gate voltage, a next stage gate voltage (VNEXT) and a clock (CLK), includes: a shift register (SR) including a plurality of stages (SRS) connected to each other by a cascade connection, each of the plurality of stages (SRS) including: a first thin film transistor (TFT) (T1) switched by the start voltage (VST) or the previous stage gate voltage and transmitting the high level power voltage (VDD) to a Q node (Q); a second TFT (T2) switched by the next stage gate voltage (VNEXT)I and transmitting the low level power voltage (VSS) to the Q node (Q); a third TFT (T8) switched by a voltage of the Q node (Q) and transmitting the clock (CLK) to an output node; and a first resistor (R1) connected between the output node and the low level power voltage (VSS).