Gate Driving Circuit Shift Register for Display Panel
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Solution Overview
Problem
Existing gate driving modules in display devices face challenges in maintaining driving capability and reliability over long use, especially when directly mounted on glass substrates, as they occupy significant space and are difficult to reduce in size without compromising performance.
Innovation Solution
A gate driving circuit with a shift register having multiple stages, each comprising a pull-up unit, pull-down unit, discharging unit, and holding unit, which generates and maintains gate signals efficiently, ensuring reliable operation by managing clock signals and gate-off voltages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a gate driving module is directly mounted on a display panel to reduce manufacturing cost and size, then the device size and cost are reduced, but the gate driving module occupies too much space in the display panel
Solution Approach 1:
The gate driving module is divided into multiple independent stages (first stage, second stage, third stage, etc.), each capable of generating gate signals independently. This segmentation allows the module to be distributed across the display panel rather than occupying a single large area, resolving the contradiction between reducing overall device size and maintaining driving capability.
Solution Approach 2:
The gate driving circuit transitions from a planar IC mounting approach to a three-dimensional integration approach by directly forming driving circuits on the glass substrate using amorphous silicon TFTs. This dimensional change enables space-efficient integration while maintaining full driving functionality.
2Area of stationary object
If the size of the gate driving module is reduced to fit more content, then the display panel area is increased, but maintaining driving capability and reliability after long use becomes difficult
Solution Approach 1:
Each stage of the gate driving module includes a holding unit that preliminarily maintains gate signals at appropriate voltage levels before they are needed. This preliminary action ensures that gate signals are ready and stable when required, maintaining driving capability and reliability even in a compact configuration.
Solution Approach 2:
The gate driving module incorporates feedback mechanisms where each stage monitors and adjusts its own operation based on signal conditions. This feedback ensures stable gate signal generation and maintains driving capability over long periods, resolving the reliability issue in compact designs.
3Ease of manufacture
If a gate driving IC is used with tape carrier package or chip-on-glass method, then manufacturing process is established, but manufacturing cost and device size cannot be sufficiently reduced
Solution Approach 1:
The gate driving circuit and display panel are merged into a single integrated structure by directly forming the driving circuit on the glass substrate. This merging eliminates the need for separate IC mounting processes and reduces overall device size while maintaining ease of manufacture through the use of amorphous silicon TFTs.
Solution Approach 2:
Instead of using a separate gate driving IC, the driving circuit is copied directly onto the glass substrate using amorphous silicon TFT fabrication processes. This copying approach integrates the driving functionality into the panel itself, reducing device size and manufacturing complexity while maintaining ease of production.
Data Source
AI summary
A gate driving circuit that may be capable of improving driving margin and maintaining reliability even after long use, and a display device having the gate driving circuit. The gate driving circuit includes a shift register having a plurality of stages dependently connected to one another, wherein each stage includes a pull-up unit outputting a first clock signal as a gate signal in response to a signal of a first node, to which a first input signal is applied, a pull-down unit discharging the gate signal to a gate-off voltage in response to a second input signal, a discharging unit discharging the signal of the first node to the gate-off voltage in response to the second input signal, and a holding unit maintaining the signal of the first node at the gate-off voltage in response to a delay signal of the first clock signal.