Gate Driving Circuit Cascade Structure Signal Delay Reduction
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Solution Overview
Problem
Existing gate driving circuits experience signal delays and transverse line observations due to inefficiencies in gate signal propagation, affecting the display quality of display devices.
Innovation Solution
A gate driving circuit with a cascade structure of driving stages, each stage comprising specific transistors and capacitors that enhance voltage levels and control signal propagation, including control transistors, output transistors, and pull-down transistors, to ensure timely and efficient gate signal output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate driving circuit is used, then the circuit structure is simple, but signal delays occur and transverse line observations appear
Solution Approach 1:
The gate driving circuit is divided into multiple driving stages (first driving stage, second driving stage, third driving stage, etc.), where each stage independently drives a corresponding gate line. This segmentation allows each stage to be optimized for signal propagation quality while maintaining overall system functionality, resolving the contradiction between reliability and complexity by distributing the driving function across multiple specialized units.
Solution Approach 2:
Each driving stage is configured with specific local characteristics: the first driving stage includes a first control transistor and first capacitor, the second driving stage includes a second control transistor and second capacitor, and so on. This local quality differentiation ensures that each stage can be optimized for its specific position in the cascade, improving overall signal propagation quality without requiring complete redesign of the entire circuit.
2Speed
If signal propagation speed is increased to reduce delays, then operating characteristics improve, but transverse line observations worsen
Solution Approach 1:
Each driving stage includes control capacitors (first capacitor, second capacitor, etc.) that pre-charge and maintain voltage levels before the actual gate signal is transmitted. This preliminary action ensures that when the signal propagates through the cascade, it maintains adequate voltage levels throughout, preventing both delays and transverse line observations caused by voltage degradation.
Solution Approach 2:
The control capacitors and control transistors in each driving stage act as intermediaries that buffer and condition the signal between successive stages. These intermediaries ensure smooth signal transitions and maintain voltage integrity, preventing the harmful effects of both signal delays and transverse line observations that would occur with direct stage-to-stage coupling.
3Loss of time
If more control transistors and capacitors are added to each driving stage, then signal delay is reduced, but device complexity increases
Solution Approach 1:
The cascade configuration ensures continuous useful action throughout the signal path, with each driving stage continuously maintaining and transmitting the gate signal. The control capacitors continuously hold voltage levels, and the control transistors continuously regulate signal flow, eliminating dead zones and reducing overall signal delay without requiring excessive components in any single stage.
Solution Approach 2:
The gate driving circuit operates in periodic cycles, with each driving stage sequentially activating its control transistors and capacitors to propel the signal through the cascade. This periodic action allows components to be reused efficiently across multiple signal cycles, reducing the need for additional components while maintaining rapid signal propagation.
Data Source
AI summary
An n-th driving stage of a gate driving circuit includes a first control transistor being configured to increase a voltage of a first node to a first voltage, a control capacitor having one end connected to the first node, a second control transistor being configured to increase the first voltage of the first node to a second voltage that is higher than the first voltage, a third control transistor being configured to increase a voltage of a second node to a third voltage when being turned on according to the voltage applied to the first node, and an output transistor being configured to output a gate signal of the n-th driving stage when being turned on according to the voltage applied to the second node.