Gate Driving Circuit Synchronized Shift Register Units
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Solution Overview
Problem
Conventional gate driving circuits in display panels face issues such as split screen and H-block due to simultaneous switching of gate integrated circuit units, leading to out-of-phase gate voltages.
Innovation Solution
A gate driving circuit with cascaded shift register units and a delay controller that synchronizes the application of gate scanning signals across pairs of shift register units, using an AND gate, timing controller, and timing counter to ensure synchronized switching and reduce the abrupt difference in gate voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate integrated circuit units switch simultaneously on both sides of the display panel, then the gate scanning signals can be applied efficiently, but it causes out-of-phase gate voltages resulting in split screen and H-block artifacts
Solution Approach 1:
The patent applies preliminary action by introducing a delay controller that pre-adjusts the timing of gate scanning signals before they reach the shift register units. The delay controller receives a delay control signal and uses it to synchronize the switching timing of gate integrated circuit units on both sides of the display panel, ensuring that voltage changes occur in phase and preventing display artifacts while maintaining efficient scanning
2Area of stationary object
If multiple gate driving integrated circuits are used to drive gate lines from both sides of the panel, then the gate scanning coverage is improved, but simultaneous switching of these circuits causes voltage instability and display defects
Solution Approach 1:
The patent introduces a delay controller as an intermediary component between the signal source and the shift register units. This intermediary receives delay control signals and uses them to coordinate the timing of multiple gate driving integrated circuits, ensuring synchronized switching that maintains voltage stability while enabling comprehensive gate line coverage across the display panel
Data Source
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AI summary
A display panel having a plurality of gate lines and a gate driving circuit for driving the plurality of gate lines, the gate driving circuit including a plurality of first cascaded shift register units (IC1) and a plurality of second cascaded shift register units (IC2) for applying gate scanning signals to gate lines connected thereto. The display panel includes a first pair of first cascaded shift register unit (IC1) and second cascaded shift register unit (IC2); a second pair of first cascaded shift register unit (IC1) and second cascaded shift register unit (IC2); the second pair adjacent to the first pair; the first cascaded shift register unit (IC1) in the first pair is electrically coupled to the second cascaded shift register unit (IC2) in the second pair; and the second cascaded shift register unit (IC2) in the first pair is electrically coupled to the first cascaded shift register unit (IC1) in the second pair; a first group of gate lines (21) connecting the first pair of first cascaded shift register unit (IC1) and second cascaded shift register unit (IC2); and a second group of gate lines (22) connecting the first cascaded shift register unit (IC1) in the first pair and the first cascaded shift register unit (IC1) in the second pair. The gate driving circuit includes a first column of cascaded shift register units and a second column of cascaded shift register units, the first column and the second column having a same number of cascaded shift register units; the first cascaded shift register unit (IC1) in the first pair is an odd numbered cascaded shift register unit in the first column, the second cascaded shift register unit (IC2) in the first pair is an odd numbered cascaded shift register unit in the second column, the first cascaded shift register unit (IC1) in the second pair is an even numbered cascaded shift register unit in the second column, and the second cascaded shift register unit (IC2) in the second pair is an even numbered cascaded shift register unit in the first column.