Gate Driving Circuit for TFT-LCD with Cascade Shift Registers
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Solution Overview
Problem
Traditional gate driving circuits for TFT-LCDs face issues with high power consumption, poor anti-interference capability, and unstable output waves due to high clock frequencies, which complicate the Chip on Glass process and reduce product reliability.
Innovation Solution
A gate driving circuit design featuring a cascade connection of shift registers with a signal outputting circuit, signal inputting circuit, inverting circuit, and logic circuit, utilizing MOS type transistors to reduce clock frequency, enhance anti-interference capability, and stabilize output waves, while using fewer transistors to decrease power consumption and production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional gate driver IC is bound to glass panel by COG process, then the gate driving function is achieved, but the manufacturing difficulty increases and product excellent rate decreases when resolution is high
Solution Approach 1:
The gate driver function is extracted from a separate IC chip and integrated directly into the array substrate through the GOA technique. This eliminates the need for COG bonding process, thereby removing the manufacturing difficulty and reliability issues associated with high-resolution displays requiring long gate driver ICs.
Solution Approach 2:
The gate driver circuit is merged with the array substrate by manufacturing the shift register transistors directly on the glass panel using the same array process. This integration combines previously separate components (gate driver IC and array substrate) into a single unified structure, simplifying manufacturing and improving reliability.
2Reliability
If a high clock frequency is used in the shift register, then the gate driving function is achieved, but the power consumption increases and anti-interference capability deteriorates
Solution Approach 1:
The circuit dynamically controls the clock signal timing through the clock transistor and level transistor, which are selectively turned on and off based on the input signal state. This dynamic operation allows the circuit to achieve gate driving functionality with reduced clock frequency requirements, thereby lowering power consumption while maintaining anti-interference capability.
Solution Approach 2:
The shift register operates using periodic clock signals (CLK1 and CLK2) that are applied in a structured sequence. By utilizing this periodic action with optimized timing, the circuit achieves efficient signal propagation without requiring excessively high clock frequencies, thus balancing power consumption and operational reliability.
3Stability of the object's composition
If a high clock frequency is used in the shift register, then the gate driving function is achieved, but the output wave stability decreases and burrs increase
Solution Approach 1:
The logic circuit performs preliminary action by holding the clock transistor in an on-state before the level transistor is turned on. This preparatory state ensures that the output terminal is properly conditioned before signal transition, preventing output instability and burrs without requiring high clock frequencies.
Solution Approach 2:
The logic circuit acts as an intermediary between the clock transistor and level transistor, coordinating their operation to ensure smooth transitions. This intermediary control mechanism prevents direct conflicts between transistor switching actions, thereby stabilizing the output wave and reducing burrs while operating at moderate clock frequencies.
4Reliability
If more transistors are used in the gate driving circuit, then the circuit functionality is enhanced, but the power consumption and production cost increase
Solution Approach 1:
Each transistor in the shift register is designed to perform multiple functions. For example, the clock transistor serves both as a signal transmission gate and as part of the logic circuit for controlling the level transistor. This multi-functionality reduces the total number of transistors needed while maintaining complete circuit functionality, thereby lowering power consumption and production costs.
Data Source
AI summary
A gate driving circuit and a display, the gate driving circuit comprises a plurality of shift register connected in cascade. The shift register comprises: a signal outputting circuit (32), a signal inputting circuit (31), an inverting circuit (33) and a logic circuit (33). The signal outputting circuit (32) receives a forward direction clock signal from an external circuit and comprises a clock transistor and a level transistor. The signal outputting circuit outputs the forward direction clock signal when the clock transistor is turned on and outputs a constant-low level signal when the level transistor is turned on. The signal inputting circuit (31) receives an output signal from a previous shift register, and turns on the clock transistor when the received output signal of the previous shift register is valid. The inverting circuit (33) receives an inverse direction clock signal from the external circuit, turns off the clock transistor and turns on the level transistor at the same time when the inverse direction clock signal is valid. The logic circuit (33) holds the clock transistor as being turned on before the level transistor is turned on. The gate driving circuit has low power consumption, strong capability of anti-interference and a stable output wave.