Gate Driving Circuit Voltage Sequencing for Narrow-Bezel Displays

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Solution Overview

Problem

The large size of transistors in gate driving circuits, particularly the pull-down node control transistors, occupies excessive space in the bezel area of display panels, hindering narrow bezel design.

Innovation Solution

The gate driving circuit includes a pull-up node control circuit, a pull-down node control circuit, and a gate driving output circuit, where the pull-down node control transistor receives a fixed voltage signal lower than the control voltage signal, reducing the gate-source voltage difference and current driving capability, allowing for a reduction in transistor size and bezel area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the transistor area is increased to improve driving capability, then the driving capability is improved, but the bezel area increases

Engineering Contradiction:
Improvedriving capabilityVSAvoidbezel area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent applies parameter changes by adjusting the gate-source voltage difference through voltage signal sequencing. In the first output stage, a first voltage signal is applied to the gate, while in the second output stage, a second voltage signal is applied. This dynamic voltage adjustment optimizes the transistor's driving capability without requiring excessive transistor area, thereby reducing the bezel area while maintaining necessary driving performance.

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If the transistor size is reduced to minimize bezel area, then the bezel area is reduced, but the driving capability decreases

Engineering Contradiction:
Improvebezel areaVSAvoiddriving capability
Core Design Contradiction:
Area of stationary objectVSPower

Solution Approach 1:

The patent employs dynamics by implementing sequential voltage signaling across two output stages. The control circuit dynamically switches voltage signals to the gate of the pull-down node control transistor between the first and second output stages. This dynamic control allows the transistor to achieve sufficient driving capability during active periods while maintaining a smaller transistor size, thus reducing bezel area without compromising performance.

Inventive Principle:
Principle #15Dynamics

3Area of moving object

If the gate-source voltage difference is reduced to decrease current driving capability, then the transistor size can be reduced, but the current driving capability decreases

Engineering Contradiction:
Improvetransistor sizeVSAvoidcurrent driving capability
Core Design Contradiction:
Area of moving objectVSPower

Solution Approach 1:

The patent implements periodic action through sequential output stages. In the first output stage, a first voltage signal is applied to the gate, and in the second output stage, a second voltage signal is applied. This periodic voltage switching allows the transistor to operate with reduced gate-source voltage difference during certain periods, enabling smaller transistor size, while still providing sufficient current driving capability during active driving periods when the appropriate voltage signal is applied.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250252890A1Gate driving circuit, driving method, display panel, and display device
Publication Date: 2025.08.07 XIAMEN TIANMA OPTOELECTRONICS CO LTD
  • US20250252890A1 patent drawing
  • US20250252890A1 patent drawing
  • US20250252890A1 patent drawing

AI summary

A gate driving unit of a gate driving circuit includes a pull-up node control circuit configured to control a potential of a pull-up node, a pull-down node control circuit including a pull-down node control transistor electrically connected to a pull-down node, and a gate driving output circuit configured to control a gate driving signal under the control of voltage signals of the pull-up node and the pull-down node. The pull-down node control circuit controls the potential of a pull-down node under the control of a control voltage signal, a fixed voltage signal, and a voltage signal of the pull-up node. The control voltage signal of the gate is less than the fixed voltage signal of the drain of the pull-down node control transistor, or the fixed voltage signal of the gate is less than the control voltage signal of the drain of the pull-down node control transistor.