Gate Driving Circuit Voltage Control for Transistor Burnout Prevention
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Solution Overview
Problem
Transistors in display panels deteriorate due to continuous voltage application, leading to burnout and reduced performance.
Innovation Solution
A gate driving circuit with a specific voltage control mechanism that includes a high period and a low period in the gate signal, where the low period has a first level that gradually falls to a second level, helping to prevent transistor burnout by de-trapping electrons in the insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a continuous voltage is applied to the gate lines to maintain display operation, then the display function is sustained, but the transistors in the pixels deteriorate and burn out over time
Solution Approach 1:
The gate signal is designed with periodic voltage variations including a high period for normal display operation and a low period with a gradually falling voltage level. This periodic action allows electrons trapped in the insulating layer to be de-trapped during the low period, preventing transistor deterioration while maintaining display functionality during the high period.
2Illumination intensity
If a high voltage level is maintained in the gate signal to ensure display performance, then the display quality is maintained, but electrons become trapped in the insulating layer causing transistor burnout
Solution Approach 1:
The gate signal incorporates periodic low periods with gradually falling voltage levels that enable electron de-trapping from the insulating layer. This periodic reduction in voltage prevents cumulative electron trapping while maintaining high voltage levels during display operation, thus preserving both display quality and transistor health.
Solution Approach 2:
The low period with gradually falling voltage is introduced as a preventive measure before transistor burnout occurs. This preliminary anti-action counteracts the harmful electron trapping effect by creating conditions that facilitate electron de-trapping, thereby preventing the accumulation of trapped electrons that would lead to transistor failure.
3Reliability
If the gate signal voltage level is reduced to prevent transistor deterioration, then transistor lifespan is extended, but the display quality and brightness are compromised
Solution Approach 1:
The gate signal alternates between high voltage periods for optimal display quality and low voltage periods for transistor protection. During high periods, full brightness and display quality are maintained, while during low periods with gradually falling voltage, electron de-trapping occurs to prevent transistor deterioration, achieving both goals through temporal separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents transistor burnout and deterioration, ensuring stable operation and extended lifespan by managing voltage levels and electron trapping in the transistors.
Implementation Method 1
Electrons trapped in the insulating layer may be de-trapped in the first period
Data Source
AI summary
A display device includes a display panel which includes a plurality of gate lines and a plurality of pixels, where each of the pixels is connected to a corresponding gate line among the gate lines, and a gate driving circuit which includes a stage that applies a gate signal to at least one of the gate lines. The gate signal includes a high period in which the gate signal has a high voltage and a low period in which the gate signal has a low voltage having a level less than a level of the high voltage, and the low period includes a falling period in which the low voltage falls to a second level from a first level which is greater than the second level.