Gate Driving Circuit Voltage Control for Display Panels
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Solution Overview
Problem
In display devices, the performance of transistors in gate driving circuits deteriorates when high voltage is applied, leading to delayed gate signals due to the lack of effective control over voltage levels and discharge mechanisms in existing gate driving circuits.
Innovation Solution
The proposed gate driving circuit incorporates multiple driving stages with specific transistors and capacitors to control voltage levels and discharge mechanisms, including first and second control transistors, and pull-down parts to manage gate and carry signals efficiently, ensuring accurate and timely signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage is applied to transistors in gate driving circuits, then the driving capability is improved, but transistor performance deteriorates and gate signals are delayed
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitor C1 to a high voltage level (ELVDD) before the transistor needs to operate. This allows the transistor to switch with reduced voltage stress during actual operation, preventing performance deterioration while maintaining driving capability. The capacitor is charged in advance through the transistor M1 when the first node is at low level, so that when the transistor needs to drive the gate signal, the capacitor is already ready to supply the necessary charge without requiring the transistor to sustain high voltage continuously.
2Power
If high voltage is applied to transistors in gate driving circuits, then the driving capability is improved, but gate signal transmission speed decreases
Solution Approach 1:
The capacitor C1 is pre-charged to high voltage level before the gate signal needs to be transmitted. This preliminary charging action ensures that when the transistor switches, the capacitor can immediately discharge to provide the necessary current boost, enabling fast signal transmission without requiring the transistor to operate continuously at high voltage which would cause delays.
Solution Approach 2:
The circuit employs periodic action through the alternating charging and discharging cycles of capacitor C1. The capacitor is charged during one phase (when first node is low) and discharged during another phase (when first node goes high), creating a rhythmic pattern that efficiently transfers energy. This periodic charge-discharge mechanism ensures that the transistor experiences reduced stress during actual signal transmission while still achieving fast switching speeds through the capacitor's rapid discharge.
3Reliability
If voltage control mechanisms are added to gate driving circuits, then transistor performance is maintained, but circuit complexity increases
Solution Approach 1:
The capacitor C1 serves multiple functions: it acts as a charge storage element, a voltage regulation component, and a signal coupling device. By making the capacitor multi-functional, the circuit achieves voltage control to maintain transistor performance without adding separate dedicated control circuits, thus minimizing the increase in overall circuit complexity.
Solution Approach 2:
The circuit implements self-service through the automatic charge-discharge cycle of capacitor C1. The capacitor automatically charges when the first node is at low level and discharges when the first node goes high, without requiring external control mechanisms. This self-regulating behavior provides voltage control to maintain transistor performance while avoiding the need for additional complex control circuits.
Data Source
AI summary
A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.