Power Semiconductor Gate Driving for Low-Loss High-Current Switching
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Solution Overview
Problem
Existing methods for controlling power semiconductor elements increase switching time and loss when large currents flow, which is not addressed by previous literature.
Innovation Solution
A driving circuit with a first gate voltage control circuit and a second gate voltage control circuit that controls gate voltage in different manners across four time regions to reach a mirror voltage, adjusting to the magnitude of the main current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the current change rate (dl/dt) is reduced to reduce electromagnetic interference (EMI), then EMI is reduced, but switching time increases which in turn increases switching loss
Solution Approach 1:
The gate voltage application process is divided into multiple distinct stages with different voltage slopes. The first stage applies a first slope to rapidly reach the Miller Plateau, the second stage applies a second slope with reduced slope to reach threshold voltage, and the third stage applies a third slope greater than the second slope when the switch is substantially fully turned on. This segmentation allows optimization of each stage independently to balance EMI reduction with switching loss minimization
Solution Approach 2:
The gate voltage application uses dynamic, time-varying slopes rather than a constant slope. The slope is adjusted according to the switching phase and current magnitude, allowing the system to adaptively optimize the trade-off between EMI reduction and switching speed. When large current flows, the controlled reduction of current change rate during specific phases reduces EMI while maintaining acceptable switching performance
2Object-affected harmful factors
If control to reduce the current change rate is applied when large current flows, then electromagnetic interference is reduced, but switching time increases
Solution Approach 1:
The switching process is segmented into three distinct time regions with different control strategies. The first region rapidly reaches the Miller Plateau, the second region carefully controls the current change rate to reduce EMI, and the third region completes the switching with appropriate speed. This segmentation allows EMI reduction during the critical second region while maintaining overall switching efficiency
Solution Approach 2:
The gate voltage slope parameter is dynamically changed based on the switching phase and current magnitude. During the second time region when large current flows, the slope is reduced to control the current change rate and reduce EMI. The slope is then increased in the third region to complete switching efficiently, thus managing the trade-off between EMI reduction and switching time
Data Source
AI summary
In a driving circuit for a power semiconductor element, a first gate voltage control circuit controls a gate voltage of the semiconductor element in response to a turn-on command, in a first time region, a second time region, and a third time region in order, in different manners for the respective time regions, to thereby cause a gate voltage to reach mirror voltage. The gate voltage reaches the mirror voltage in the second time region or the third time region according to magnitude of a main current flowing through the power semiconductor element. A second gate voltage control circuit controls the gate voltage greater than or equal to the mirror voltage.