Multi-Stage Gate Driving Circuit for Stable Low-Power Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices face challenges in stably outputting gate signals at low power consumption, which affects the efficiency and performance of the driving circuit.
Innovation Solution
The driving circuit incorporates a design with multiple stages, each comprising transistors and capacitors that utilize phase-shifted clock signals to stabilize gate signal output, ensuring non-overlapping voltage levels and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional gate driving circuits are used, then gate signals can be output, but power consumption increases and signal stability deteriorates
Solution Approach 1:
The gate driving circuit is divided into multiple stages, where each stage includes a first transistor for input signal reception and a second transistor for output signal generation. This segmentation allows independent optimization of each stage's power consumption and signal stability characteristics, resolving the contradiction between low power consumption and stable signal output.
2Reliability
If clock signal voltage levels are increased to improve signal stability, then gate signal stability improves, but power consumption increases
Solution Approach 1:
Different voltage levels are applied to different clock signal lines locally. Specifically, a first clock signal with voltage levels between a first voltage and a third voltage is applied to the first transistor gate, while a second clock signal with voltage levels between a first voltage and a second voltage is applied to the second transistor gate. This local differentiation optimizes signal stability at each location without uniformly increasing overall power consumption.
3Reliability
If multiple transistors are added to improve signal stability, then gate signal stability improves, but device complexity increases
Solution Approach 1:
Each stage of the gate driving circuit uses a universal structure with a first transistor for input signal reception and a second transistor for output signal generation, controlled by clock signals. This multi-functional design achieves signal stability through systematic transistor coordination rather than adding complex specialized components, resolving the contradiction between reliability and device complexity.
Data Source
AI summary
Each of a plurality of stages of a driving circuit includes a first transistor connected to an input terminal, to which a start signal is input, and a first node and including a gate connected to a first clock terminal, to which a first clock signal is input, and a second transistor connected to a first output terminal and a second clock terminal, to which a second clock signal is input, and including a gate connected to the first node. The second clock signal swings between a first voltage and a second voltage lower than the first voltage, and the first clock signal swings between the first voltage and a third voltage lower than the second voltage.