Gate Driving Circuit With Time-Division Scan Lines for Narrow Bezel LCDs
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Solution Overview
Problem
In liquid crystal display technology, achieving a narrow bezel is challenging, especially as the number of pixels increases, as existing gate on panel (GOP) technologies struggle to reduce the bezel width below 1 millimeter.
Innovation Solution
A gate driving circuit with multiple cascade-connected modules, each driving two scan lines in a time-division manner, reduces the number of gate driving modules and connecting lines, thereby minimizing the circuit area and bezel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional GOP technology is used to drive scan lines, then the display panel can be manufactured, but the bezel width cannot be reduced below 1 millimeter
Solution Approach 1:
The patent combines the driving functions for two adjacent scan lines into a single gate driving module. Each module controls two scan lines (Sn and Sn+1) by sharing common transistors and using time-division multiplexing of clock signals, thereby reducing the total number of gate driving modules by approximately half compared to traditional GOP technology where each scan line has its own dedicated module.
Solution Approach 2:
The gate driving module is designed with multi-functionality to drive multiple scan lines. The same physical module structure and transistor components can sequentially drive different scan lines by switching clock signals, making a single module serve multiple purposes and reducing overall circuit complexity.
2Area of stationary object
If the number of gate driving modules is reduced, then the bezel width decreases, but the circuit area must be optimized
Solution Approach 1:
Adjacent gate driving modules share common transistors (such as the 17th transistor connecting nodes N1 and N2, and the 18th transistor connecting nodes N3 and N4) and other circuit components. This sharing of resources reduces the total transistor count and circuit area occupied by the gate driving circuit, enabling further bezel narrowing.
Solution Approach 2:
The patent introduces time-division multiplexing in the temporal dimension to drive multiple scan lines sequentially. By using different clock phases (first clock signal for even scan lines, second clock signal for odd scan lines), the circuit achieves multi-line driving capability without proportionally increasing physical circuit area.
3Productivity
If more scan lines are driven simultaneously, then the display resolution increases, but the number of required gate driving modules increases
Solution Approach 1:
The patent employs periodic clock signals with different phases to sequentially activate different scan lines. The first clock signal drives even-numbered scan lines during one phase, while the second clock signal drives odd-numbered scan lines during another phase, creating a periodic scanning pattern that increases effective driving capacity without requiring proportional increases in hardware.
Solution Approach 2:
The gate driving module dynamically switches between driving different scan lines based on the phase of the clock signals. The module can adaptively control which scan line is active at any given moment, enabling flexible and efficient utilization of the driving circuit resources to handle increased scan line quantities.
Data Source
AI summary
A gate driving circuit which allows narrower framing of a display screen includes cascade-connected gate driving modules. Each gate driving module is electrically coupled to first and second scan lines and outputs scanning signals to the first and the second scan lines in a time-division manner in response to first and second clock signals. Each gate driving module includes an input transistor, and first and second output transistors. The input transistor receives a trigger signal for activating the gate driving module. The input transistor controls the first output transistor to output first scanning signal to first scan line in response to the first clock signal and controls the second output transistor to output second scanning signal to the second scan line in response to the second clock signal.