Gate Driving Circuit with Parallel Transistors for Voltage Loss
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Solution Overview
Problem
Existing gate driving circuits face challenges in stably outputting gate signals due to voltage loss and threshold voltage issues, which affect the performance of display apparatuses.
Innovation Solution
The gate driving circuit incorporates a first node controller with a first transistor and a second transistor in parallel to compensate for voltage loss and a second node controller to control the voltage of a pull-up transistor, utilizing P-type and N-type transistors with specific voltage levels and connections to stabilize signal output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single transistor is used to transfer the start signal, then the circuit complexity is reduced, but voltage loss occurs due to threshold voltage
Solution Approach 1:
The patent combines a first transistor and a second transistor in parallel to form a combined transistor structure. This merged structure transfers the start signal together, allowing the threshold voltages to be compensated for each other, thereby reducing overall voltage loss while maintaining relatively simple circuit complexity.
Solution Approach 2:
The patent changes the parameters of the transistors by using different transistor types (first transistor with first threshold voltage, second transistor with second threshold voltage) and adjusting their widths. This parameter optimization allows the combined structure to achieve threshold voltage compensation, reducing voltage loss during signal transfer.
2Loss of energy
If transistor width is increased to reduce threshold voltage impact, then voltage loss is reduced, but device area increases
Solution Approach 1:
The patent optimizes transistor parameters by carefully selecting the widths of the first and second transistors. Instead of simply increasing the width of a single transistor, the patent uses two transistors with specifically designed width ratios to achieve threshold voltage compensation, thereby reducing voltage loss without excessive area increase.
Solution Approach 2:
The patent creates a composite transistor structure by combining two different transistor types in parallel. This composite structure leverages the complementary characteristics of the transistors to achieve threshold voltage compensation, providing an efficient solution that balances voltage loss reduction with area constraints.
3Reliability
If threshold voltage compensation is implemented, then signal stability is improved, but device complexity increases
Solution Approach 1:
The patent merges two transistors in parallel to create a combined transistor structure that inherently provides threshold voltage compensation. This approach achieves signal stability improvement without requiring complex external compensation circuits, thereby limiting the increase in device complexity.
Solution Approach 2:
The combined transistor structure performs self-compensation of threshold voltage through its internal configuration. The first and second transistors work together to automatically compensate for voltage loss during signal transfer, eliminating the need for external compensation mechanisms and keeping the device complexity manageable.
Data Source
AI summary
A gate driving circuit is provided. Each stage of the gate driving circuit includes a first node controller configured to control a voltage level of a first node connected to a gate of a pull-down transistor, and a second node controller configured to control a voltage level of a second node connected to a gate of a pull-up transistor, wherein the first node controller comprises a first circuit and a second circuit, wherein the first circuit is connected between the first node and an input terminal to which a start signal is input, and configured to transfer the start signal to the first node, and the second circuit is connected between the input terminal and the first node, and may be configured to boost a voltage level of a voltage of the first node.