Gate Driving Circuit Timing to Reduce PBTS in TFT Stages
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Solution Overview
Problem
Thin film transistors in gate driving circuits experience positive bias temperature stress (PBTS) due to continuous turn-on states during emission periods, leading to driving failure and reduced reliability.
Innovation Solution
A gate driving circuit design that includes a Q-node controller, QB-node controller, pull-up and pull-down transistors, and inverter transistors controlled by clock signals to manage transistor voltages, preventing continuous turn-on states and thereby reducing PBTS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor is continuously turned on during emission period, then the gate driving circuit can maintain stable output voltage, but positive bias temperature stress (PBTS) occurs leading to driving failure
Solution Approach 1:
The patent applies periodic action by controlling the transistor to switch between on and off states in a periodic manner during the emission period. The transistor is turned on during the first sub-emission period and turned off during the second sub-emission period, creating a periodic switching pattern that prevents continuous conduction and reduces PBTS accumulation while maintaining display output.
2Reliability
If transistor switching is implemented to reduce PBTS, then reliability improves, but circuit complexity increases
Solution Approach 1:
The emission period is segmented into multiple sub-emission periods (first sub-emission period and second sub-emission period). This segmentation allows the transistor to be controlled in discrete time intervals, switching on during the first sub-period and off during the second sub-period, thereby reducing PBTS while maintaining a relatively simple circuit structure.
Solution Approach 2:
The transistor is controlled to switch periodically between on and off states during the emission period. This periodic switching action reduces PBTS accumulation by preventing continuous conduction, while the control mechanism remains integrated within the existing gate driving circuit architecture, avoiding excessive complexity.
Data Source
AI summary
A gate driving circuit includes a Q-node controller configured to control a voltage of a Q-node by first and second clock signals and a start signal or an output signal of an upstream stage, a QB-node controller configured to control a voltage of a QB-node by the second clock signal, a pull-up transistor configured to pull-up drive a logic output terminal in response to the voltage of the Q-node, a pull-down transistor configured to pull-down drive the logic output terminal in response to the voltage of the QB-node, a first inverter transistor configured to supply a gate-low voltage to an output terminal in response to the first clock signal, and a second inverter transistor configured to supply a gate-high voltage to the output terminal in response to a voltage of the logic output terminal.