Gate Driving Circuit Pull-Down Mechanism for Signal Falling Time
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Solution Overview
Problem
Traditional gate driving circuits in display devices have long falling time periods for gate driving signals, leading to incorrect voltage levels being written into pixels, which affects display data accuracy.
Innovation Solution
A gate driving circuit with a series of shift registers, where each nth shift register includes a driving circuit and a pull-down circuit that utilizes the (n−m)th and (n+m)th gate signals to speed up the discharging of the output terminal to a low voltage level, reducing the falling time period of the gate signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional shift register architecture is used, then the gate driving circuit can provide gate driving signals, but the falling time periods of the pulses become too long causing incorrect voltage levels to be written into pixels
Solution Approach 1:
The gate driving circuit is segmented into multiple shift registers coupled in series, where each shift register is further divided into a driving circuit and a pull-down circuit. This segmentation allows independent optimization of each module's function, enabling the pull-down circuit to specifically address the falling time issue without affecting the driving circuit's operation.
Solution Approach 2:
The pull-down circuit is activated in advance to prepare for the falling edge of the gate signal. By receiving the (n−m)th and (n+m)th gate signals ahead of time, the pull-down circuit can immediately begin discharging the output terminal when needed, reducing the falling time period and ensuring correct voltage levels are written into pixels.
2Manufacturing precision
If the falling time periods are shortened using pull-down circuit, then voltage level accuracy improves, but circuit complexity increases
Solution Approach 1:
The pull-down circuit is designed to serve multiple purposes: it accelerates the falling edge of gate signals, works across all shift registers in the series, and can be controlled by multiple gate signals ((n−m)th and (n+m)th) to handle both forward and reverse scanning modes. This multi-functionality justifies the added complexity by providing comprehensive benefits across the entire gate driving circuit.
Solution Approach 2:
The pull-down circuit is nested within each shift register structure, with the driving circuit and pull-down circuit forming a hierarchical organization. This nesting allows the pull-down functionality to be integrated into the existing shift register architecture without requiring a complete redesign, thereby limiting the increase in overall circuit complexity.
Data Source
AI summary
A gate driving circuit includes a plurality of shift registers coupled in series. An nth shift register includes a driving circuit and a pull-down circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a first clock signal and output a gate signal according to the first clock signal. The pull-down circuit is electrically coupled to the output node. The pull-down circuit is configured to receive an (n−m)th gate signal and an (n+m)th gate signal, and pull-down the gate signal to a low voltage level according to one of the (n−m)th gate signal and the (n+m)th gate signal, wherein m and n are positive integers.