Gate Driving Circuit With Auxiliary Pull-Down Timing Control
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Solution Overview
Problem
The conventional Gate Driver on Array (GOA) circuit's pull-down maintaining transistor experiences threshold voltage shift due to continuous operation, leading to abnormal gate signals and reduced display quality.
Innovation Solution
A gate driving circuit with a first auxiliary module controlling the on/off state of the pull-down maintaining transistor to prevent prolonged activation, utilizing a first auxiliary transistor to manage the gate voltage of the pull-down maintaining transistor, thereby maintaining the correct gate signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pull-down maintaining transistor is continuously working to maintain the gate voltage at low level, then the gate voltage maintenance function is improved, but the threshold voltage shifts causing abnormal gate signal output
Solution Approach 1:
The patent implements periodic action by introducing a control signal that periodically turns off the pull-down maintaining transistor after it has maintained the gate voltage at low level for a predetermined period. This prevents continuous operation-induced threshold voltage shift while ensuring the gate voltage is maintained at the correct level during the active period, thus resolving the contradiction between maintenance reliability and signal accuracy.
Solution Approach 2:
The patent employs feedback mechanisms where the control signal is generated based on the operational state of the pull-down maintaining transistor and the gate voltage level. This feedback control ensures the transistor operates long enough to maintain the gate voltage but turns off before threshold voltage shift occurs, balancing reliability and accuracy requirements.
2Reliability
If the pull-down maintaining transistor operates for a long time to ensure proper gate voltage maintenance, then the display quality is improved, but the transistor may not normally maintain the gate voltage at late stage due to threshold voltage shift
Solution Approach 1:
The patent applies periodic action by controlling the pull-down maintaining transistor to operate for a predetermined optimal duration, then turning it off. This prevents excessive operation that would cause threshold voltage shift and failure to maintain gate voltage, while ensuring sufficient operation to maintain display quality during the active period.
Solution Approach 2:
The patent implements preliminary action by pre-establishing the optimal operation duration through control signal timing before the threshold voltage shift problem occurs. The control signal is designed to turn off the transistor after the predetermined time, preventing the late-stage failure mode while ensuring early-stage proper functionality.
Data Source
AI summary
Embodiments of the present disclosure are directed to a gate driving circuit and a display panel. The gate driving circuit includes a plurality of cascaded gate driving units. Each of the gate driving unit includes a pull-up control module, a pull-up module electrically connected to the pull-up control module through a first node and electrically connected to a scan line, a pull-down module electrically connected to the scan line, and a first pull-down maintaining module. The first pull-down maintaining module includes a first auxiliary module and a first pull-down maintaining transistor having a drain connected to the first node. The first auxiliary module, electrically connected to a gate of the first pull-down maintaining transistor, and configured to control an on/off state of the first pull-down maintaining transistor.