Gate Driving Circuit Q-Node Control for Output Buffer Consistency

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Solution Overview

Problem

Existing gate driving circuits in flat panel displays experience output deviations in the first and last output buffer circuits, leading to potential malfunctions and image quality degradation due to uneven voltage changes in the Q node during overlapping driving.

Innovation Solution

Incorporating a first output improvement circuit to reinforce the voltage of the Q node before the first output buffer circuit operates and a second output improvement circuit to attenuate the voltage after the last output buffer circuit, using transistors and capacitors to manage the node voltage effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If one stage circuit outputs gate signals to multiple pixel lines through multiple output buffer circuits, then the gate driving circuit size is reduced, but output deviation occurs in the first and last output buffer circuits

Engineering Contradiction:
Improvegate driving circuit sizeVSAvoidoutput deviation
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies local quality by providing special output improvement circuits only for the first and last output buffer circuits, which are the circuits experiencing output deviation. The intermediate output buffer circuits do not require these improvement circuits. This targeted approach addresses the specific problem locations without adding unnecessary complexity to the entire system.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The output improvement circuits perform preliminary anti-action by pre-charging the Q node voltage before the first output buffer circuit operates and maintaining voltage levels after the last output buffer circuit. This preemptive voltage management prevents output deviation before it occurs, rather than correcting it after the fact.

Inventive Principle:
Principle #9Preliminary anti-action

2Device complexity

If the Q node voltage is not pre-charged before the first output buffer circuit, then the circuit operation is simple, but output deviation occurs in the first output buffer circuit

Engineering Contradiction:
Improvecircuit operation complexityVSAvoidoutput deviation
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements preliminary action by pre-charging the Q node voltage through the output improvement circuit before the first output buffer circuit begins operation. This pre-charging ensures that the first output buffer circuit starts with the correct voltage conditions, preventing output deviation and ensuring reliable gate signal output to the first pixel line.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If the Q node voltage is not maintained after the last output buffer circuit, then the circuit operation is simple, but output deviation occurs in the last output buffer circuit

Engineering Contradiction:
Improvecircuit operation complexityVSAvoidoutput deviation
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The output improvement circuit implements feedback by monitoring the operation status of the last output buffer circuit and adjusting the Q node voltage accordingly. When the last output buffer circuit completes its operation, the improvement circuit maintains or adjusts the voltage level to prevent output deviation, ensuring consistent gate signal output across all pixel lines.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250218395A1Gate Driving Circuit and Display Device Including the Same
Publication Date: 2025.07.03 LG DISPLAY CO LTD
  • US20250218395A1 patent drawing
  • US20250218395A1 patent drawing
  • US20250218395A1 patent drawing

AI summary

A gate driving circuit and a display device including the same are disclosed. More particularly, a gate driving circuit capable of improving an output deviation of a first output buffer circuit and an output deviation of a last output buffer circuit among a plurality of output buffer circuits included in one stage circuit, respectively and a display device including the same are disclosed.