Gate Driving Circuit With QB-Node Precharge for Stable Scanning

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Solution Overview

Problem

Display devices suffer from image abnormalities and deteriorated image quality due to malfunctions in the gate driving circuit, particularly during non-driving periods, and unwanted leakage currents in transistor operations.

Innovation Solution

A gate driving circuit with an inverter circuit structure that prevents malfunctions and leakage currents by controlling the QB node charging transistor, utilizing a scan pull-up and pull-down transistor, and a control circuit to manage voltage states during non-driving periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional gate driving circuit is used, then the circuit structure is simple, but malfunctions occur during non-driving periods causing image abnormalities

Engineering Contradiction:
Improvecircuit reliabilityVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The inverter circuit is configured to perform preliminary charging and discharging actions on the QB node before the actual scanning operation. During the non-driving period, the inverter circuit pre-charges the QB node through the first transistor when the first control node is high, and pre-discharges it through the second transistor when the first control node is low, ensuring the node is in the correct state before driving begins and preventing malfunctions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The inverter circuit acts as an intermediary between the control circuit and the scan output buffer. It introduces intermediate control nodes (Q node, QB node) that mediate the signal transmission, allowing for controlled charging and discharging of the scan output node during different periods without directly exposing the simple circuit structure to malfunctioning conditions

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the scan output buffer is controlled directly, then the circuit is simple, but leakage current occurs in the transistor

Engineering Contradiction:
Improveleakage current preventionVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control of the scan output buffer is segmented into distinct phases: a non-driving period for charging/discharging the QB node and a driving period for actual scanning. The inverter circuit segments the control function by using separate transistors (first and second transistors) for charging and discharging operations, preventing simultaneous conduction that would cause leakage current while maintaining simple overall circuit structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The inverter circuit implements feedback control by continuously monitoring the voltage state of the QB node and adjusting the charging/discharging operations accordingly. When the QB node reaches the expected voltage level, the corresponding transistor turns off, preventing excessive leakage current. This feedback mechanism ensures reliable operation without requiring complex control circuits

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12406616B2Gate driving circuit and display panel
Publication Date: 2025.09.02 LG DISPLAY CO LTD
  • US12406616B2 patent drawing
  • US12406616B2 patent drawing
  • US12406616B2 patent drawing

AI summary

Embodiments of the disclosure relate to a gate driving circuit and a display panel, which may prevent malfunctions without causing any circuit issue during a non-driving period when the scan signal line is not driven by including a scan output buffer including a scan pull-up transistor and a scan pull-down transistor and outputting a first scan signal and a control circuit configured to control the scan output buffer and including a first transistor for charging a QB node and two or more transistors connected between a gate node of the first transistor and a low-potential node to which a low-potential voltage is applied.