Gate Driving Circuit Resolution Control via Mode Switching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional gate driving circuits for display technology lack the flexibility to control display resolution in different areas of a display panel effectively.

Innovation Solution

A gate driving circuit with a plurality of driving units connected in cascade, where each driving unit includes N shift register units and a mode control circuit. The mode control circuit receives a control signal to connect the shift register units in one of multiple resolution modes, allowing for flexible control of display resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional gate driving circuits use fixed cascade connection of shift registers, then the circuit structure is simple, but the display resolution control flexibility is poor

Engineering Contradiction:
Improvedisplay resolution control flexibilityVSAvoidcircuit structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic reconfiguration of shift register connections through mode control circuits that can switch between cascade and parallel connections based on control signals. This allows the gate driving circuit to adapt its resolution control flexibility dynamically while maintaining a relatively simple base circuit structure.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The mode control circuits enable the same shift register units to serve multiple functions by switching between cascade connection (for high resolution) and parallel connection (for low resolution). This multi-functionality resolves the contradiction by allowing one circuit structure to achieve both simplicity and adaptability across different operating modes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If shift register units are connected in cascade for high resolution, then the display resolution is high, but the scanning time increases

Engineering Contradiction:
Improvedisplay resolutionVSAvoidscanning time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system dynamically switches between cascade and parallel connection modes depending on the required resolution and timing requirements. When high resolution is needed, cascade connection is used; when scanning speed is prioritized, parallel connection is activated, thus resolving the time-resolution tradeoff.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the connection configuration parameter of shift register units based on operational requirements. By adjusting the connection mode (cascade or parallel) as a controllable parameter, the system can optimize between resolution and scanning time for different display scenarios.

Inventive Principle:
Principle #35Parameter changes

3Speed

If shift register units are connected in parallel for fast scanning, then the scanning speed is fast, but the display resolution decreases

Engineering Contradiction:
Improvescanning speedVSAvoiddisplay resolution
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The mode control circuits enable shift register units to function in both parallel and cascade configurations, allowing the same hardware to achieve fast scanning when needed while maintaining the capability for high resolution when required, thus resolving the speed-resolution contradiction.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12236824B2Gate driving circuit, method of driving gate driving circuit, and display panel
Publication Date: 2025.02.25 BOE TECHNOLOGY GROUP CO LTD
  • US12236824B2 patent drawing
  • US12236824B2 patent drawing
  • US12236824B2 patent drawing

AI summary

The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.