Gate Driving Circuit Timing to Prevent LCD Ripple Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate driving circuits for liquid crystal displays suffer from voltage ripples during the transition time of the input clock, leading to inadequate holding of the gate voltage at the off-voltage level due to signal delays, which affects the output characteristics.
Innovation Solution
The proposed gate driving circuit incorporates an inverter that controls the holding transistor based on an inverter clock, which precedes the input clock by a predetermined time interval, ensuring the output timing of the off-voltage is synchronized to prevent ripple voltage generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a holding transistor is used to hold the gate voltage at the off-voltage level, then the gate voltage can be maintained during the (n-1)H period, but signal delay prevents the holding transistor from responding in time to prevent ripple voltage
Solution Approach 1:
The inverter clock is designed to precede the input clock by a predetermined time interval, causing the holding transistor to be turned off in advance before the input clock transitions. This preliminary action ensures that the gate voltage is held at the off-voltage level before ripple voltage can occur, eliminating the timing issue caused by signal delay in the conventional circuit.
2Device complexity
If the holding transistor is controlled by the input clock directly, then the control logic is simple, but the transistor cannot turn off in time to prevent ripple voltage due to signal delay
Solution Approach 1:
An inverter clock signal is introduced as an intermediary between the input clock and the holding transistor control. This intermediary signal is generated by inverting the input clock, providing a timing reference that allows the holding transistor to be controlled with proper timing margins, thus preventing ripple voltage while maintaining clear and manageable control logic.
3Reliability
If the inverter clock precedes the input clock by a predetermined time interval, then the holding transistor turns off in time to prevent ripple voltage, but the circuit timing becomes more complex
Solution Approach 1:
The timing parameter of the inverter clock is specifically designed to precede the input clock by a predetermined time interval that matches the signal delay characteristics of the circuit. By optimizing this time interval parameter, the circuit achieves reliable ripple voltage prevention while keeping the timing complexity manageable through a single adjustable parameter rather than multiple coordinated timing signals.
Data Source
AI summary
A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.